AD7946 Analog Devices, AD7946 Datasheet - Page 16

• Manufacturer Part Number: AD7946
• Manufacturer: Analog Devices

Specifications of AD7946

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 500kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7946
0V TO 4.096V
DIGITAL INTERFACE
Although the AD7946 has a reduced number of pins, it offers
flexibility in its serial interface modes.
The AD7946, when in CS mode, is compatible with SPI, QSPI™,
digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or
ADSP-219x. This interface can use either 3-wire or 4-wire. A
3-wire interface using the CNV, SCK, and SDO signals mini-
mizes wiring connections useful, for instance, in isolated
applications. A 4-wire interface using the SDI, CNV, SCK, and
SDO signals allows CNV, which initiates the conversions, to be
Figure 32. Example of a Single-Supply Application Circuit
ADA4841
>5.2V
100nF
100nF
2.7nF
33Ω
ADR364
10µF
IN+
IN–
GND
REF
AD7946
100nF
VDD
SCK
SDO
CNV
VIO
SDI
Rev. A | Page 16 of 24
independent of the readback timing (SDI). This is useful in low
jitter sampling or simultaneous sampling applications.
The AD7946, when in chain mode, provides a daisy chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The operating mode depends on the SDI level when the CNV
rising edge occurs. CS mode is selected if SDI is high, and chain
mode is selected if SDI is low. The SDI hold time is such that
when SDI and CNV are connected, the chain mode is always
selected.
In either mode, the AD7946 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a BUSY signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a BUSY indicator,
the user must time out the maximum conversion time prior to
readback.
BUSY indicator feature is enabled
•
•
In CS mode, if CNV or SDI is low when the ADC
conversion ends (see Figure 36 and Figure 40).
In chain mode, if SCK is high during the CNV rising edge
(see Figure 44).