AD7946 Analog Devices, AD7946 Datasheet - Page 18

• Manufacturer Part Number: AD7946
• Manufacturer: Analog Devices

Specifications of AD7946

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 500kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7946
CS MODE 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7946 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 35, and the
corresponding timing is given in Figure 36.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV could be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time and
held low until the maximum conversion time to guarantee the
generation of the BUSY signal indicator. When the conversion
is complete, SDO goes from high impedance to low. With a
pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data reading controlled by the
digital host. The AD7946 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
SDI = 1
CNV
ACQUISITION
SCK
SDO
CONVERSION
Figure 36. CS Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High)
t
CONV
t
CNVH
1
t
t
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HSDO
DSDO
D13
t
2
CYC
ACQUISITION
D12
t
3
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
15
earlier, SDO returns to high impedance.
If multiple AD7946s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
ACQ
th
SCK falling edge, or when CNV goes high, whichever is
t
SCKL
VIO
t
SCKH
13
SDI
Figure 35. CS Mode 3-Wire with BUSY Indicator
t
AD7946
SCK
CNV
SCK
14
D1
Connection Diagram (SDI High)
SDO
15
D0
VIO
47kΩ
t
DIS
CONVERT
DATA IN
IRQ
CLK
DIGITAL HOST