AD7946 Analog Devices, AD7946 Datasheet - Page 7

• Manufacturer Part Number: AD7946
• Manufacturer: Analog Devices

Specifications of AD7946

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 500kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
1
AI = analog input, DI = digital input, DO = digital output, and P = power.
Mnemonic
REF
VDD
IN+
IN−
GND
CNV
SDO
SCK
SDI
VIO
Figure 4. 10-Lead MSOP Pin Configuration
GND
VDD
REF
IN+
IN–
1
2
3
4
5
(Not to Scale)
Type
AI
P
AI
AI
P
DI
DO
DI
DI
P
AD7946
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1
Description
Reference Input Voltage. The REF range is from 0.5 V to VDD, and is referred to the GND pin. This pin
should be decoupled closely to the pin with a 10 μF capacitor.
Power Supply.
Analog Input. It is referred to IN−. The voltage range, that is, the difference between IN+ and IN−,
is 0 V to REF.
Analog Input Ground Sense. Connect to the analog ground plane or to a remote sense ground.
Power Supply Ground.
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode, chain, or CS. In CS mode, it enables the SDO pin when low. In chain mode,
the data should be read when CNV is high.
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of the
ADC as follows:
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V,
3 V, or 5 V).
10
9
8
7
6
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital
data level on SDI is output on SDO with a delay of 14 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can
enable the serial output signals when low, and if SDI or CNV is low when the conversion is complete,
the BUSY indicator feature is enabled.
VIO
SDI
SCK
SDO
CNV
Rev. A | Page 7 of 24
Figure 5. 10-Lead QFN (LFCSP) Pin Configuration
GND
VDD
REF
IN+
IN–
1
2
3
4
5
(Not to Scale)
AD7946
TOP VIEW
10
9
8
7
6
VIO
SDI
SCK
SDO
CNV
AD7946