AD7946 Analog Devices, AD7946 Datasheet - Page 20

• Manufacturer Part Number: AD7946
• Manufacturer: Analog Devices

Specifications of AD7946

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 500kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7946
CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7946 is connected
to an SPI-compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 39, and the
corresponding timing is given in Figure 40.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the BUSY signal indicator. When
the conversion is complete, SDO goes from high impedance to
ACQUISITION
SDO
CNV
SCK
SDI
t
SSDICNV
t
HSDICNV
CONVERSION
t
CONV
Figure 40. CS Mode 4-Wire with BUSY Indicator Serial Interface Timing
t
EN
1
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t
t
HSDO
DSDO
D13
2
t
CYC
D12
low. With a pull-up on the SDO line, this transition can be used
as an interrupt signal to initiate the data readback controlled by
the digital host. The AD7946 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
15
SDO returns to high impedance.
3
ACQUISITION
th
Figure 39. CS Mode 4-Wire with BUSY Indicator Connection Diagram
SCK falling edge or SDI going high, whichever is earlier, the
t
ACQ
t
SCKL
t
SCKH
SDI
13
AD7946
t
SCK
CNV
SCK
14
D1
SDO
15
D0
VIO
47kΩ
t
DIS
CS1
CLK
CONVERT
DATA IN
IRQ
DIGITAL HOST