AD7946 Analog Devices, AD7946 Datasheet - Page 17

• Manufacturer Part Number: AD7946
• Manufacturer: Analog Devices

Specifications of AD7946

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 500kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

CS MODE 3-WIRE, NO BUSY INDICATOR
This mode is usually used when a single AD7946 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 33 and the corresponding timing is given in
Figure 34.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers, but CNV must be returned high
before the minimum conversion time and held high until the
maximum conversion time to avoid the generation of the BUSY
signal indicator. When the conversion is complete, the AD7946
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
ACQUISITION
SDI = 1
CNV
SCK
SDO
t
CNVH
CONVERSION
Figure 34. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)
t
CONV
t
EN
D13
1
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t
HSDO
D12
2
t
CYC
ACQUISITION
D11
are then clocked by subsequent SCK falling edges. The data is
valid on both SCK edges. Although the rising edge can be used
to capture the data, a digital host using the SCK falling edge
allows a faster reading rate, provided it has an acceptable hold
time. After the 14
whichever is earlier, SDO returns to high impedance.
t
3
ACQ
t
DSDO
t
VIO
SCKL
t
SCKH
12
SDI
Figure 33. CS Mode 3-Wire, No BUSY Indicator
AD7946
t
SCK
th
CNV
SCK
13
Connection Diagram (SDI High)
D1
SCK falling edge or when CNV goes high,
SDO
14
D0
t
DIS
CONVERT
DATA IN
CLK
DIGITAL HOST
AD7946