AD7452 Analog Devices, AD7452 Datasheet - Page 19

• Manufacturer Part Number: AD7452
• Description: Differential Input, 555 kSPS, 12-Bit A/D Converter in 8-Lead SOT-23
• Manufacturer: Analog Devices

Specifications of AD7452

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 555kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: SOT

SERIAL INTERFACE
Figure 2 shows a detailed timing diagram for the serial interface
of the AD7452. The serial clock provides the conversion clock
and also controls the transfer of data from the device during
conversion. CS initiates the conversion process and frames the
data transfer. The falling edge of CS puts the track-and-hold
into hold mode and takes the bus out of three-state. The analog
input is sampled and the conversion is initiated at this point.
The conversion requires 16 SCLK cycles to complete.
Once 13 SCLK falling edges have occurred, the track-and-hold
goes back into track on the next SCLK rising edge, as shown at
Point B in Figure 2. On the 16
line goes back into three-state. If the rising edge of CS occurs
before 16 SCLKs have elapsed, the conversion is terminated and
the SDATA line goes back into three-state.
The conversion result from the AD7452 is provided on the
SDATA output as a serial data stream. The bits are clocked out
on the falling edge of the SCLK input. The data stream of the
AD7452 consists of four leading zeros followed by 12 bits of
conversion data provided MSB first. The output coding is twos
complement.
Sixteen serial clock cycles are required to perform a conversion
and access data from the AD7452. CS going low provides the
first leading zero to be read in by the microcontroller or DSP.
+2.5V
–2.5V
Figure 34. Applying a Bipolar Single-Ended Input to the AD7452
0V
SCLK
V
IN
CS
R
R
t
10ns
2
R
EXTERNAL
V
REF
(2.5V)
R
0.1µF
th
1
SCLK falling edge, the SDATA
2.5V
2
5V
0V
V
V
IN+
IN–
3
AD7452
12.5(1/F
Figure 35. Serial Interface Timing Example
V
4
REF
SCLK
t
5
)
Rev. B | Page 19 of 28
5
t
CONVERT
1/THROUGHPUT
The remaining data is then clocked out on the subsequent
SCLK falling edges beginning with the second leading zero.
Thus, the first falling clock edge on the serial clock provides the
second leading zero. The final bit in the data transfer is valid on
the 16
(15
has been accessed after the 16 clock cycles, it is important to
ensure that before the next conversion is initiated, enough time
is left to meet the acquisition, and quiet time specifications (see
the Timing Example).
In applications with a slower SCLK, it may be possible to read in
data on each SCLK rising edge, i.e., the first rising edge of SCLK
after the CS falling edge would have the leading zero provided
and the 15
Timing Example
Having F
a cycle time of
A cycle consists of
Therefore, if t
This 540 ns satisfies the requirement of 290 ns for t
From Figure 35, t
where t
satisfying the minimum requirement of 60 ns.
13
th
) falling edge. Once the conversion is complete and the data
th
8
falling edge, having been clocked out on the previous
= 35 ns. This allows a value of 255 ns for t
SCLK
th
14
t
6
SCLK edge would have DB0 provided.
10 ns + 12.5(1/10 MHz) + t
= 10 MHz and a throughput rate of 555 kSPS gives
2
1/Throughput = 1/555,000 = 1.8 µs
= 10 ns
t
2
ACQ
15
+ 12.5(1/F
t
ACQUISITION
t
comprises
2.5(1/F
8
t
16
ACQ
SCLK
SCLK
= 540 ns
) + t
) + t
t
QUIET
8
ACQ
+ t
QUIET
= 1.8 µs
ACQ
= 1.8 µs
QUIET
ACQ.
AD7452
,