AD7452 Analog Devices, AD7452 Datasheet - Page 22

• Manufacturer Part Number: AD7452
• Description: Differential Input, 555 kSPS, 12-Bit A/D Converter in 8-Lead SOT-23
• Manufacturer: Analog Devices

Specifications of AD7452

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 555kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: SOT

AD7452
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7452 when not con-
verting, the average power consumption of the ADC decreases
at lower throughput rates. Figure 39 shows how, as the through-
put rate is reduced, the device remains in its power-down state
longer and the average power consumption is reduced
accordingly. It shows this for both 5 V and 3 V power supplies.
For example, if the AD7452 is operated in continuous sampling
mode with a throughput rate of 100 kSPS and an SCLK of
10 MHz, and the device is placed in power-down mode between
conversions, the power consumption is calculated as follows:
Power Dissipation during Normal Operation = 7.25 mW max
(for V
If the power-up time is one dummy cycle (1.06 µs if CS is
brought high after the 10
low after the quiet time) and the remaining conversion time is
another cycle, i.e., 1.6 µs, the AD7452 can be said to dissipate
7.25 mW for 2.66 µs
If the throughput rate = 100 kSPS, the cycle time = 10 µs and
the average power dissipated during each cycle is
For the same scenario, if V
normal operation is 3.3 mW max.
The AD7452 can now be said to dissipate 3.3 mW for 2.66 µs
during each conversion cycle.
The average power dissipated during each cycle with a
throughput rate of 100 kSPS is therefore
This is how the power numbers in Figure 39 are calculated.
For throughput rates above 320 kSPS, it is recommended that
the serial clock frequency be reduced for optimum power
performance.
∗
This figure assumes a very short time to enter power-down mode. This
increases as the burst of clocks used to enter the power-down mode is
increased.
DD
= 5 V)
(2.66/10) × 7.25 mW = 1.92 mW
(2.66/10) × 3.3 mW = 0.88 mW
∗
during each conversion cycle.
th
DD
SCLK falling edge and then brought
= 3 V, the power dissipation during
Rev. B | Page 22 of 28
∗
MICROPROCESSOR AND DSP INTERFACING
The serial interface on the AD7452 allows the part to be directly
connected to a range of different microprocessors. This section
explains how to interface the AD7452 with some of the more
common microcontroller and DSP serial interface protocols.
AD7452 to ADSP-21xx
The ADSP-21xx family of DSPs is interfaced directly to the
AD7452 without any glue logic required.
The SPORT control register should be set up as follows:
To implement power-down mode, SLEN should be set to 1001
to issue an 8-bit SCLK burst.
The connection diagram is shown in Figure 40. The ADSP-21xx
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
alternate framing mode and the SPORT control register is set
up as described. The frame synchronization signal generated on
the TFS is tied to CS and, as with all signal processing
applications, equidistant sampling is necessary. However in this
example, the timer interrupt is used to control the sampling rate
of the ADC; under certain conditions, equidistant sampling may
not be achieved.
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right-Justify Data
SLEN = 1111, 16-Bit Data-Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0
ITFS = 1
0.01
Figure 39. Power vs. Throughput Rate for Power-Down Mode
100
0.1
10
1
0
50
100
THROUGHPUT (kSPS)
150
V
DD
200
= 5V
V
DD
= 3V
250
300
350