AD7452 Analog Devices, AD7452 Datasheet - Page 9

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AD7452

Manufacturer Part Number
AD7452
Description
Differential Input, 555 kSPS, 12-Bit A/D Converter in 8-Lead SOT-23
Manufacturer
Analog Devices
Datasheet

Specifications of AD7452

Resolution (bits)
12bit
# Chan
1
Sample Rate
555kSPS
Interface
Ser,SPI
Analog Input Type
Diff-Uni
Ain Range
(2Vref) p-p
Adc Architecture
SAR
Pkg Type
SOT
Positive Gain Error
This is the deviation of the last code transition (011...110 to
011...111) from the ideal V
zero code error has been adjusted out.
Negative Gain Error
This is the deviation of the first code transition (100...000 to
100...001) from the ideal V
the zero code error has been adjusted out.
Track-and-Hold Acquisition Time
The minimum time required for the track-and-hold amplifier to
remain in track mode for its output to reach and settle to within
0.5 LSB of the applied input signal.
IN+
IN+
– V
– V
IN–
IN–
(i.e., –V
(i.e., V
REF
REF
– 1 LSB), after the
+ 1 LSB), after
Rev. B | Page 9 of 28
Power Supply Rejection Ratio (PSRR)
The ratio of the power in the ADC output at full-scale fre-
quency, f, to the power of a 100 mV p-p sine wave applied to the
ADC V
varies from 1 kHz to 1 MHz.
Pf is the power at frequency f in the ADC output; Pfs is the
power at frequency f
DD
supply of frequency f
PSRR(dB) = 10log(Pf/Pf
S
in the ADC output.
S
. The frequency of this input
S
)
AD7452

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