AD7452 Analog Devices, AD7452 Datasheet - Page 5

• Manufacturer Part Number: AD7452
• Description: Differential Input, 555 kSPS, 12-Bit A/D Converter in 8-Lead SOT-23
• Manufacturer: Analog Devices

Specifications of AD7452

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 555kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: SOT

TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
level. See Figure 2 and the Serial Interface section.
V
V
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
POWER-UP
Common-mode voltage.
Mark/space ratio for the SCLK input is 40/60 to 60/40.
Measured with the load circuit of
t
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
See
3
3
8
DD
CM
4
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of
1
2
= 2.7 V to 3.6 V, f
Power-Up Time
= V
5
REF
; T = T
A
Limit at T
10
10
16 × t
1.6
60
10
10
20
40
0.4 t
0.4 t
10
10
35
1
SDATA
SCLK
section.
CS
SCLK
SCLK
MIN
SCLK
SCLK
to T
t
t
2
3
MIN
= 10 MHz, f
MAX
, T
Figure 3
0
MAX
, unless otherwise noted.
1
4 LEADING ZEROS
0
and defined as the time required for the output to cross 0.8 V or 2.4 V with V
Unit
kHz min
MHz max
µs max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs max
S
= 555 kSPS, V
2
0
3
t
4
Description
t
Minimum quiet time between the end of a serial read and the next falling edge of CS
Minimum CS pulse width
CS falling edge to SCLK falling edge setup time
Delay from CS falling edge until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK high pulse width
SCLK low pulse width
SCLK edge to data valid hold time
SCLK falling edge to SDATA three-state enabled
SCLK falling edge to SDATA three-state enabled
Power-up time from full power-down
0
SCLK
Figure 2. Serial Interface Timing Diagram
REF
= 1/f
4
DB11
= 2.0 V; V
t
5
SCLK
Rev. B | Page 5 of 28
5
t
DB10
t
7
CONVERT
DD
= 4.75 V to 5.25 V, f
13
B
DB2
8
14
t
, quoted in the Timing Specifications is the true bus relinquish
6
DB1
SCLK
= 10 MHz, f
15
Figure 3.
t
DB0
8
DD
DD
= 5 V, or 0.4 V or 2.0 V for V
The measured number is then extrapolated
) and timed from a 1.6 V voltage
16
THREE-STATE
S
= 555 kSPS, V
t
QUIET
t
1
REF
= 2.5 V;
DD
= 3 V.
AD7452