AD9866 Analog Devices, AD9866 Datasheet - Page 19

• Manufacturer Part Number: AD9866
• Manufacturer: Analog Devices

Specifications of AD9866

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Nibble
• Analog Input Type: Diff-Uni
• Ain Range: 6.3 V p-p,8 mV p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

SERIAL PORT
Table 10. SPI Register Mapping
Address
(Hex)
SPI PORT CONFIGURATION AND SOFTWARE RESET
0x00
POWER CONTROL REGISTERS (VIA PWR_DWN PIN)
0x01
0x02
HALF-DUPLEX POWER CONTROL
0x03
PLL CLOCK MULTIPLIER/SYNTHESIZER CONTROL
0x04
0x05
0x06
1
Bit
Break-
down
(7)
(6)
(5)
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
(7:3)
(2)
(1)
(0)
(5)
(4)
(3:2)
(1:0)
(2)
(1)
(0)
(7:6)
(5)
(4)
(3:2)
(1)
(0)
Description
4-Wire SPI
LSB First
S/W Reset
Clock Syn.
TxDAC/IAMP
Tx Digital
REF
ADC CML
ADC
PGA Bias
RxPGA
CLK Syn.
TxDAC/IAMP
Tx Digital
REF
ADC CML
ADC
PGA Bias
RxPGA
Tx OFF Delay
Rx _TXEN
Tx PWRDN
Rx PWRDN
Duty Cycle Enable
f
PLL Divide-N
PLL Multiplier-M
OSCIN to RXCLK
Invert RXCLK
Disabled RXCLK
CLKOUT2 Divide
CLKOUT2 Invert
CLKOUT2 Disable
CLKOUT1 Divide
CLKOUT1 Invert
CLKOUT1 Disable
ADC
from PLL
Width
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
1
1
1
1
1
2
2
1
1
1
2
1
1
2
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0xFF
0
0
00
01
0
0
0
01
0
01
0
0
CONFIG = 0
MODE = 0 (Half-Duplex)
Rev. B | Page 19 of 48
Power-Up Default Value
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0xFF
0
0
00
10*
0
0
0
01
0
0
01
0
0
CONFIG = 1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
N/A
0
0
00
01
0
0
0
01
0
0
01
0
0
CONFIG = 0
MODE = 1 (Full-Duplex)
0
0
0
0
0
0
0
0
0
0
0
1*
1
1
1
1
1
1
1
N/A
0
0
00
01
1*
0
0
01
0
1*
01
0
1*
CONFIG = 1
Comments
Default SPI configuration is
3-wire, MSB first.
PWR_DWN = 0.
Default setting is for all
blocks powered on.
PWR_DWN = 1.
Default setting* is for all
functional blocks powered
down except PLL.
*MODE = CONFIG = 1.
Setting has PLL powered
down with OSCIN input
routed to RXCLK output.
Default setting is for TXEN
input to control power
on/off of Tx/Rx path.
Tx driver delayed by 31
1/f
Default setting is Duty Cycle
Restore disabled, ADC CLK
from OSCIN input, and PLL
multiplier × 2 setting.
*PLL multiplier × 4 setting.
Full-duplex RXCLK normally
at nibble rate.
*Exception on power-up.
Default setting is CLKOUT2
and CLKOUT1 enabled with
divide-by-2.
*CLKOUT1 and CLKOUT2
disabled.
DATA
clock cycles.
AD9866