AD9866 Analog Devices, AD9866 Datasheet - Page 20

• Manufacturer Part Number: AD9866
• Manufacturer: Analog Devices

Specifications of AD9866

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Nibble
• Analog Input Type: Diff-Uni
• Ain Range: 6.3 V p-p,8 mV p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9866
Address
(Hex)
Rx PATH CONTROL
0x07
0x08
Tx/Rx PATH GAIN CONTROL
0x09
0x0A
Tx AND Rx PGA CONTROL
0x0B
Tx DIGITAL FILTER AND INTERFACE
0x0C
Rx INTERFACE AND ANALOG/DIGITAL LOOPBACK
0x0D
DIGITAL OUTPUT DRIVE STRENGTH, TxDAC OUTPUT, AND REV ID
0x0E
0x0F
1
Bit
Break-
down
(5)
(4)
(0)
(7:0)
(6)
(5:0)
(6)
(5:0)
(6)
(5)
(3)
(2)
(1)
(7:6)
(4)
(2)
(1)
(0)
(7)
(6)
(5)
(4)
(2)
(1)
(0)
(7)
(0)
(3:0)
Description
Initiate Offset Cal.
Rx Low Power
Rx Filter ON
Rx Filter Tuning
Cutoff Frequency
Use SPI Rx Gain
Rx Gain Code
Use SPI Tx Gain
Tx Gain Code
PGA Code for Tx
PGA Code for Rx
Force GAIN strobe
Rx Gain on Tx Port
3-Bit RxPGA Port
Interpolation
Factor
Invert
TXEN/TXSYNC
LS Nibble First*
TXCLK neg. edge
Twos complement
Analog Loopback
Digital Loopback*
Rx Port 3-State
Invert
RXEN/RXSYNC
LS Nibble First*
RXCLK neg. edge
Twos complement
Low Drive
Strength
TxDAC Output
REV ID Number
Width
1
1
1
8
1
6
1
6
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
4
0
0
1
0x80
0x00
0x7F
0
1
0
0
0
01
0
N/A
0
0
0
0
N/A
0
N/A
0
0
0
0
0x00
CONFIG = 0
MODE = 0 (Half-Duplex)
Rev. B | Page 20 of 48
Power-Up Default Value
0
1*
1
0x61
0x00
0x7F
0
1
0
0
1**
00
0
N/A
0
0
0
0
N/A
0
N/A
0
0
0
0
0x00
CONFIG = 1
0
0
1
0x80
0x00
0x7F
0
1
0
1*
0
01
0
0
0
1
0
0
0
0
0
0
1
0
0
0x00
CONFIG = 0
MODE = 1 (Full-Duplex)
0
1*
1
0x80
0x00
0x7F
0
1
0
1*
0
01
0
0
0
1
0
0
0
0
0
0
1
0
0
0x00
CONFIG = 1
Comments
Default setting has LPF ON
and Rx path at nominal
power bias setting.
*Rx path to low power.
Refer to Low-Pass Filter
section.
Default setting is for hardware
Rx gain code via PGA or Tx
data port.
Default setting is for Tx gain
code via SPI control.
Default setting is RxPGA
control active.
*Tx port with GAIN strobe
(AD9875/AD9876
compatible).
**3-bit RxPGA gain map
(AD9975 compatible).
Default setting is 2× interpo-
lation with LPF response.
Data format is straight binary
for half-duplex and twos
complement for full-duplex
interface.
*Full-duplex only.
Data format is straight
binary for half-duplex and
twos complement for full-
duplex interface.
Analog loopback: ADC Rx
data fed back to TxDAC.
Digital loopback: Tx input
data to Rx output port.
*Full-duplex only.
Default setting is for high
drive strength and IAMP
enabled.