AD9866 Analog Devices, AD9866 Datasheet - Page 35

• Manufacturer Part Number: AD9866
• Manufacturer: Analog Devices

Specifications of AD9866

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Nibble
• Analog Input Type: Diff-Uni
• Ain Range: 6.3 V p-p,8 mV p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

T
formula to compensate for the RxPGA gain setting on f
This
increased. Applications that need to maintain a minimum cut-
off frequency, f
determine the scaling factor for the highest RxPGA gain setting
to be used. Next, the f
factor to normalize to the 0 dB RxPGA gain setting (f
Equation 8 can then be used to calculate the target value.
The LPF frequency response shows a slight sensitivity to
temperature, as shown in Figure 74. Applications sensitive t
temperature drift can recalibrate the LPF by rewriting the targ
value to Register 0x08.
A
The AD9866 features a 12-bit analog-to-digital converte
capable of up to 80 MSPS. Referring to Figure 68, the ADC is
driven by the SPGA stage, which performs both the sample-
and-hold and the fine gain adjust functions. A buffer amplifier
(not shown) isolates the last CPGA gain stage from the dynamic
load presented by the SPGA stage. The full-scale input span of
the ADC is 2 V p-p, and depending on the PGA gain setting,
the full-scale input span into the SPGA is adjustable from 1 V t
2 V in 1 dB increments.
A pipelined multistage A
sample rates while consuming low power. The ADC distributes
the conversion over several smaller A/D subblocks, refining the
conversion with progressively higher accuracy as it passes the
results from stage to stage on each clock edge. The ADC typi-
cally performs best when driven internally by a 50% duty cycle
clock. This is especially the case when operating the ADC at
high sample rate (55 MSPS to 80 MSPS) and/or lower interna
bias levels, which adversely affect interstage settling time
requirements.
The ADC samp
restorer circuit, which ensures that the ADC gets a near 50%
he following scaling factor can be applied to the previous
Figure 74. Temperature Drift of f
NALOG-TO-DIGITAL CONVERTER (ADC)
Scale Factor = 1 − (RxPGA in dB)/382
scaling factor reduces the calculated f
35
30
25
20
15
96
112
−3 dB_MIN
ling clock path also includes a duty cycle
128
TARGET-DECIMAL EQUIVALENT
−3 dB_MIN
, for all RxPGA gain settings should first
144
DC architecture is used to achieve high
F
OUT
F
OUT
−3 dB
F
160
should be divided by this scale
ACTUAL 80MHz AND –40 ° C
OUT
ACTUAL 80MHz AND +25 ° C
for f
ACTUAL 80MHz AND +85 ° C
176
ADC
= 80 MSPS and RxPGA = 0 dB
192
−3
dB
208
as the RxPGA
224
r (ADC)
−3 dB_0 dB
−3 dB
240
:
o
).
Rev. B | Page 35 of 48
is
(9)
l
et
o
duty cycle clock even when presented with a clock source
poor symmetry (35/65). This circuit should be enabled, if the
ADC sampling clock is a buffered version of the reference signal
appearing at OSCIN (see the Clock Synthesizer section) and if
this reference signal is derived from an oscillator or crystal whose
specified symmetry cannot be guaranteed to be within 45/55
(or 55/45). This circuit can remain disabled, if the ADC
sampling clock is derived from a divided down version of the
clock synthesizer’s VCO, because this clock is near 50%.
The ADC’s power consumption can be reduced by 25 mA, with
minimal effect on its performance, by setting Bit 4 of Registe
Alternative power bias settings are also available via Register 0x13
as discussed in the Power Control and Dissipation section.
Lastly, the ADC can be completely powered down for half-
duplex operation, further reducing the AD9866’s peak powe
consumption.
The ADC has an internal voltage reference and reference a pli-
fier as shown i
generates a stable 1 V reference level that is converted to a dif-
ferential 1 V reference centered about mid-supply (AVDD/2
The outputs of the differential reference amplifier are available
at the REFT and REFB pins and must be properly decoupled fo
optimum performance. The REFT and REFB pins are conven-
iently situated at the corners of the CSP package such that C1
(0603 type) can be placed directly across its pins. C3 and C4 ca
be placed underneath C1, and C2 (10 μF tantalum) can be
placed furthest from the package.
Table 21. SPI Registers for Rx ADC
Address (Hex)
0x04
0x07
0x13
n Figure 75. The internal band gap r
Figure 75. ADC Reference and Decoupling
1.0V
Bit
(5)
(4)
(4)
(2:0)
VIEW
TOP
ADCs
TO
Description
Duty cycle restore circuit
ADC clock from PLL
ADC low power mode
ADC power bias adju
REFT
REFB
C1
C4
C1
0.1μF
C2
C3
C3
0.1μF
C4
0.1μF
eference
st
AD9866
C2
10μF
r 0x07.
with
m
r
).
,
r
n