AD9866 Analog Devices, AD9866 Datasheet - Page 22

• Manufacturer Part Number: AD9866
• Manufacturer: Analog Devices

Specifications of AD9866

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Nibble
• Analog Input Type: Diff-Uni
• Ain Range: 6.3 V p-p,8 mV p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9866
When the SPI LSB first bit is set high, the serial port interprets
both instruction and data bytes LSB first. Multibyte data trans-
fers in LSB format can be completed by writing an instruction
byte that includes the register address of the first address to be
accessed. The AD9866 automatically increments the address for
each successive byte required for the multibyte communication
cycle.
Figure 46 illustrates the timing requirements for a write opera-
tion to the SPI port. After the serial port enable ( SEN ) signal
goes low, data (SDIO) pertaining to the instruction header is
read on the rising edges of the clock (SCLK). To initiate a write
operation, the read/not-write bit is set low. After the instruction
header is read, the eight data bits pertaining to the specified
register are shifted into the SDIO pin on the rising edge of the
next eight clock cycles. If a multibyte communication cycle is
specified, the destination address is decremented (MSB first)
and shifts in another eight bits of data. This process repeats
until all the bytes specified in the instruction header (N1, N0
bits) are shifted into the SDIO pin. SEN must remain low
during the data transfer operation, only going high after the last
bit is shifted into the SDIO pin.
SDATA
SDATA
SCLK
SCLK
SEN
SEN
Figure 45. SPI Timing, MSB First (Upper) and LSB First (Lower)
A0
R/W N1
A1
INSTRUCTION CYCLE
INSTRUCTION CYCLE
N2
A2
A3
A4
A4
A3
N2
A2
N1
A1
R/W
A0
D0 1 D1 1
D7 1 D6 1
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
D6 N
D1 N D0 N
D7 N
Rev. B | Page 22 of 48
SCLK
Figure 47 illustrates the timing for a 3-wire read operation to
the SPI port. After SEN goes low, data (SDIO) pertaining to the
instruction header is read on the rising edges of SCLK. A read
operation occurs if the read/not-write indicator is set high.
After the address bits of the instruction header are read, the
eight data bits pertaining to the specified register are shifted out
of the SDIO pin on the falling edges of the next eight clock
cycles. If a multibyte communication cycle is specified in the
instruction header, a similar process as previously described for
a multibyte SPI write operation applies. The SDO pin remains
three-stated in a 3-wire read operation.
SCLK
Figure 48 illustrates the timing for a 4-wire read operation to
the SPI port. The timing is similar to the 3-wire read operation
with the exception that data appears at the SDO pin, while the
SDIO pin remains high impedance throughout the operation.
The SDO pin is an active output only during the data transfer
phase and remains three-stated at all other times.
SCLK
SDIO
SDIO
SDO
SDIO
SEN
SEN
SEN
t
t
DS
DS
t
DS
Figure 47. SPI 3-Wire Read Operation Timing
Figure 48. SPI 4-Wire Read Operation Timing
t
t
t
t
t
t
HI
S
S
S
HI
Figure 46. SPI Write Operation Timing
HI
1/
1/
1/
R/W
R/W
R/W
f
t
t
t
f
f
DH
DH
DH
SCLK
SCLK
SCLK
N1
N1
t
t
t
LOW
N1
LOW
LOW
A2
A2
N0
A1
A1
A0
A0
A0
t
t
DV
DV
D7
D7
D7
D6
D6
D6
D1
D1
D1
D0
D0
t
H
D0
t
t
t
EZ
EZ
EZ