AD9866 Analog Devices, AD9866 Datasheet - Page 24

• Manufacturer Part Number: AD9866
• Manufacturer: Analog Devices

Specifications of AD9866

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Nibble
• Analog Input Type: Diff-Uni
• Ain Range: 6.3 V p-p,8 mV p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9866
Figure 52 shows a half-duplex interface with the AD9866 acting
as the master, generating all the required clocks. CLKOUT1
provides a clock equal to the bus data rate that is fed to the
ASIC as well as back to the TXCLK and RXCLK inputs. This
interface has the advantage of reducing the digital ASIC’s pin
count by three. The ASIC needs only to generate a bus control
signal that controls the data flow on the bidirectional bus.
FULL-DUPLEX MODE
The full-duplex mode interface is selected when the MODE pin
is tied high. It can be used for full- or half-duplex applications.
The digital interface port is divided into two 6-bit ports called
Tx[5:0] and Rx[5:0], allowing simultaneous Tx and Rx opera-
tions for full-duplex applications. In half-duplex applications,
the Tx[5:0] port can also be used to provide a fast update of the
RxPGA (AD9876 backward compatible) during an Rx opera-
tion. This feature is enabled by default and can be used to
reduce the required pin count of the ASIC (refer to RxPGA
Control section for details).
In either application, Tx and Rx data are transferred between
the ASIC and AD9866 in 6-bit nibbles at twice the internal
input/output word rates of the Tx interpolation filter and ADC.
Note that the TxDAC update rate must not be less than the
nibble rate. Therefore, the 2× or 4× interpolation filter must be
used with a full-duplex interface.
DIGITAL ASIC
DIGITAL ASIC
Data[11:0]
BUS_CTR
Figure 51. Example of a Half-Duplex Digital Interface
Figure 52. Example of a Half-Duplex Digital Interface
Data[11:0]
DAC_CLK
ADC_CLK
CLKOUT
Tx/Rx
CLKIN
Tx/Rx
RXEN
TXEN
with AD9866 Serving as the Master
with AD9866 Serving as the Slave
FROM
CRYSTAL
OR MASTER CLK
ADIO
[11:0]
RXEN
TXEN
TXCLK
RXCLK
CLKOUT1
OSCIN
RXEN
TXEN
TXCLK
RXCLK
OSCIN
[11:0]
ADIO
AD9866
AD9866
12
12
12
12
TO
Tx DIGITAL
FILTER
FROM
Rx ADC
TO
Tx DIGITAL
FILTER
FROM
Rx ADC
Rev. B | Page 24 of 48
The AD9866 acts as the master, providing RXCLK as an output
clock that is used for the timing of both the Tx[5:0] and Rx[5:0]
ports. RXCLK always runs at the nibble rate and can be inverted
or disabled via an SPI register. Because RXCLK is derived from
the clock synthesizer, it remains active, provided that this func-
tional block remains powered on. A buffered version of the
signal appearing at OSCIN can also be directed to RXCLK by
setting Bit 2 of Register 0x05. This feature allows the AD9866 to
be completely powered down (including the clock synthesizer)
while serving as the master.
The Tx[5:0] port operates in the following manner with the SPI
register default settings. Two consecutive nibbles of the Tx data are
multiplexed together to form a 10-bit data-word in twos complement
format. The clock appearing on the RXCLK pin is a buffered version
of the internal clock used by the Tx[5:0] port’s input latch with a
frequency that is always twice the ADC sample rate (2 × f
from the Tx[5:0] port is read on the rising edge of this sampling
clock, as illustrated in the timing diagram shown in Figure 53.
Note, TXQUIET must remain high for the reconstructed Tx data to
appear as an analog signal at the output of the TxDAC or IAMP.
The TXSYNC signal is used to indicate to which word a nibble
belongs. While TXSYNC is low, the first nibble of every word is
read as the most significant nibble. The second nibble of that
same word is read on the following TXSYNC high level as the
least significant nibble. If TXSYNC is low for more than one
clock cycle, the last transmit data is read continuously until
TXSYNC is brought high for the second nibble of a new trans-
mit word. This feature can be used to flush the interpolator
filters with zeros. Note that the GAIN signal must be kept low
during a Tx operation.
The Rx[5:0] port operates in the following manner with the SPI
register default settings. Two consecutive nibbles of the Rx data
are multiplexed together to form a 12-bit data-word in twos
complement format. The Rx data is valid on the rising edge of
RXCLK, as illustrated in the timing diagram shown in Figure 54.
The RXSYNC signal is used to indicate to which word a nibble
belongs. While RXSYNC is low, the first nibble of every word is
transmitted as the most significant nibble. The second nibble of
that same word is transmitted on the following RXSYNC high
level as the least significant nibble.
TXSYNC
RXCLK
Tx[5:0]
Figure 53. Tx[5:0] Port Full-Duplex Timing Diagram
Tx0LSB
Tx1MSB
Tx1LSB
t
DS
Tx2MSB
t
DH
Tx 2 LSB
Tx2LSB
Tx3MSB
ADC
). Data