ADUC834 Analog Devices, ADUC834 Datasheet - Page 13

• Manufacturer Part Number: ADUC834
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 62kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC834

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 4
• Other: PWM

MEMORY ORGANIZATION
The ADuC834 contains four different memory blocks, namely:
• 62 Kbytes of On-Chip Flash/EE Program Memory
• 4 Kbytes of On-Chip Flash/EE Data Memory
• 256 bytes of General-Purpose RAM
• 2 Kbytes of Internal XRAM
(1) Flash/EE Program Memory
The ADuC834 provides 62 Kbytes of Flash/EE program
memory to run user code. The user can choose to run code from
this internal memory or run code from an external program
memory.
If the user applies power or resets the device while the EA pin is
pulled low externally, the part will execute code from the external
program space; otherwise, if EA is pulled high externally, the
part defaults to code execution from its internal 62 Kbytes of
Flash/EE program memory.
Unlike the ADuC824, where code execution can overflow from
the internal code space to external code space once the PC
becomes greater than 1FFFH, the ADuC834 does not support
the rollover from F7FFH in internal code space to F800H in
external code space. Instead, the 2048 bytes between F800H
and FFFFH will appear as NOP instructions to user code.
Permanently embedded firmware allows code to be serially
downloaded to the 62 Kbytes of internal code space via the
UART serial port while the device is in-circuit. No external
hardware is required.
56 Kbytes of the program memory can be reprogrammed during
runtime; thus the code space can be upgraded in the field using
a user defined protocol or it can be used as a data memory.
This will be discussed in more detail in the Flash/EE Memory
section of the data sheet.
(2) Flash/EE Data Memory
4 Kbytes of Flash/EE Data Memory are available to the user
and can be accessed indirectly via a group of registers mapped
into the Special Function Register (SFR) area. Access to the
Flash/EE Data memory is discussed in detail later as part of the
Flash/EE Memory section in this data sheet.
(3) General-Purpose RAM
The general-purpose RAM is divided into two separate memories,
namely the upper and the lower 128 bytes of RAM. The lower
128 bytes of RAM can be accessed through direct or indirect
addressing; the upper 128 bytes of RAM can only be accessed
through indirect addressing as it shares the same address space
as the SFR space, which can only be accessed through direct
addressing.
The lower 128 bytes of internal data memory are mapped as
shown in Figure 2. The lowest 32 bytes are grouped into four
banks of eight registers addressed as R0 through R7. The next
GENERAL NOTES PERTAINING TO THIS DATA SHEET
1. SET implies a Logic 1 state and CLEARED implies a Logic 0 state unless
2. SET and CLEARED also imply that the bit is set or automatically cleared by
3. User software should not write 1s to reserved or unimplemented bits as they may
4. Any pin numbers used throughout this data sheet refer to the 52-lead MQFP
REV. A
otherwise stated.
the ADuC834 hardware unless otherwise stated.
be used in future products.
package, unless otherwise stated.
–13–
16 bytes (128 bits), locations 20H through 2FH above the register
banks, form a block of directly addressable bit locations at bit
addresses 00H through 7FH. The stack can be located anywhere
in the internal memory address space, and the stack depth can
be expanded up to 2048 bytes.
Reset initializes the stack pointer to location 07H. Any CALL
or PUSH pre-increments the SP before loading the stack.
Therefore, loading the stack starts from locations 08H, which is
also the first register (R0) of register bank 1. Thus, if one is
going to use more than one register bank, the stack pointer should
be initialized to an area of RAM not used for data storage.
(4) Internal XRAM
The ADuC834 contains 2 Kbytes of on-chip extended data
memory. This memory, although on-chip, is accessed via the
MOVX instruction. The 2 Kbytes of internal XRAM are
mapped into the bottom 2 Kbytes of the external address space
if the CFG834.0 bit is set. Otherwise, access to the external
data memory will occur just like a standard 8051.
Even with the CFG834.0 bit set, access to the external XRAM
will occur once the 24-bit DPTR is greater than 0007FFH.
Figure 2. Lower 128 Bytes of Internal Data Memory
BITS IN PSW
SELECTED
BANKS
VIA
FFFFFFH
000000H
Figure 3. Internal and External XRAM
11
10
01
00
CFG834.0 = 0
EXTERNAL
ADDRESS
MEMORY
SPACE)
SPACE
(24-BIT
30H
20H
18H
10H
08H
00H
DATA
7FH
2FH
1FH
17H
0FH
07H
FFFFFFH
0007FFH
000000H
000800H
GENERAL-PURPOSE
AREA
BIT-ADDRESSABLE
(BIT ADDRESSES)
FOUR BANKS OF EIGHT
REGISTERS
R0–R7
ADuC834
RESET VALUE OF
STACK POINTER
CFG834.0 = 1
EXTERNAL
ADDRESS
2 KBYTES
MEMORY
ON-CHIP
SPACE)
SPACE
(24-BIT
DATA
XRAM