ADUC834 Analog Devices, ADUC834 Datasheet - Page 70

• Manufacturer Part Number: ADUC834
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 62kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC834

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 4
• Other: PWM

ADuC834
TIMING SPECIFICATIONS
Parameter
CLOCK INPUT (External Clock Driven XTAL1)
NOTES
1
2
3
4
5
6
AC inputs during testing are driven at DV
for a Logic 0 as shown in Figure 70.
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the
loaded V
C
ADuC834 internal PLL locks onto a multiple (384 times) the external crystal frequency of 32.768 kHz to provide a stable 12.583 MHz internal clock for the system.
The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.
This number is measured at the default Core_Clk operating frequency of 1.57 MHz.
ADuC834 Machine Cycle Time is nominally defined as 12/Core_Clk.
LOAD
t
t
t
t
t
1/t
t
t
CK
CKL
CKH
CKR
CKF
CORE
CYC
CORE
for Port0, ALE, PSEN outputs = 100 pF; C
OH
/V
OL
level occurs as shown in Figure 70.
XTAL1 Period
XTAL1 Width Low
XTAL1 Width High
XTAL1 Rise Time
XTAL1 Fall Time
ADuC834 Core Clock Frequency
ADuC834 Core Clock Period
ADuC834 Machine Cycle Time
DV
DD
– 0.5V
0.45V
DD
– 0.5 V for a Logic 1, and 0.45 V for a Logic 0. Timing measurements are made at V
1, 2, 3
0.2DV
0.2DV
TEST POINTS
LOAD
Figure 70. Timing Waveform Characteristics
DD
DD
(AV
all specifications T
for all other outputs = 80 pF unless otherwise noted.
– 0.1V
+ 0.9V
t
CKH
DD
5
= 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV
6
4
Figure 69. XTAL1 Input
32.768 kHz External Crystal
MIN
Min
0.098
0.95
–70–
t
V
to T
CKL
LOAD
MAX
V
V
LOAD
LOAD
, unless otherwise noted.)
Typ
30.52
6.26
6.26
9
9
0.636
7.6
t
– 0.1V
+ 0.1V
CKR
t
CK
Max
12.58
122.45
DD
REFERENCE
= 2.7 V to 3.6 V or 4.75 V to 5.25 V;
POINTS
TIMING
t
CKF
Unit
MHz
V
V
s
s
s
s
s
s
s
LOAD
LOAD
IH
min for a Logic 1, and V
– 0.1V
+ 0.1V
V
LOAD
Figure
69
69
69
69
69
REV. A
IL
max