ADUC834 Analog Devices, ADUC834 Datasheet - Page 16

• Manufacturer Part Number: ADUC834
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 62kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC834

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 4
• Other: PWM

ADuC834
COMPLETE SFR MAP
Figure 6 shows a full SFR memory map and the SFR contents
after RESET. NOT USED indicates unoccupied SFR loca-
tions. Unoccupied locations in the SFR address space are not
FFH
F7H
EFH
E7H
DFH
D7H
CFH
C7H
BFH
B7H
AFH
A7H
9FH
97H
8FH
87H
RDY0
PRE3
SM0
ISPI
MDO
TF2
TF1
CY
RD
EA
NOTES
1
2
CALIBRATION COEFFICIENTS ARE PRECONFIGURED AT POWER-UP TO FACTORY CALIBRATED VALUES.
THESE SFRS MAINTAIN THEIR PRERESET VALUES AFTER A RESET IF TIMECON.0 = 1.
0
0 F6H
0 EEH
0 E6H
0
0
0
0
0
1
0
1
0
1 96H
0
1 86H
FEH
DEH
D6H
CEH
C6H
BEH
B6H
AEH
A6H
9EH
8EH
WCOL
PADC
EADC
EXF2
PRE2
MDE
RDY1
SM1
TR1
WR
AC
SFR MAP KEY:
SFR NOTE:
SFRs WHOSE ADDRESSES END IN 0H OR 8H ARE BIT-ADDRESSABLE.
0
0 F5H
0 EDH
0 E5H
0
0
0
0
0
1
0
1
0
1 95H
0
1 85H
BIT MNEMONIC
BIT BIT ADDRESS
RESET DEFAULT
BIT VALUE
FDH
DDH
D5H
CDH
C5H
BDH
B5H
ADH
A5H
9DH
8DH
RCLK
PRE1
SPE
SM2
MCO
CAL
PT2
ET2
TF0
F0
T1
0
0 F4H
0 ECH
0 E4H
0
0
0
0 C4H
0
1
0
1 A4H
0
1 94H
0
1 84H
FCH
NOXREF
DCH
D4H
CCH
BCH
B4H
ACH
9CH
8CH
SPIM
TCLK
PRE0
REN
TR0
MDI
RSI
PS
ES
T0
Figure 6. Special Function Register Locations and Their Reset Default Values
0
0 F3H
0
0 E3H
0
0
0
1
0
1
0
1 A3H
0
1 93H
0
1 83H
FBH
EBH
DBH
D3H
CBH
C3H
BBH
B3H
ABH
9BH
8BH
CPOL
EXEN2
ERR0
THESE BITS ARE CONTAINED IN THIS BYTE.
WDIR
INT1
I2CM
RS0
PT1
ET1
TB8
IE1
0 F2H
0 E2H
1 92H
1 82H
0
0 EAH
0
0
0
0
0
1
0
1 A2H
0
0
89H
FAH
DAH
D2H
CAH
C2H
BAH
B2H
AAH
9AH
8AH
CPHA
I2CRS
INT0
RB8
IE0
ERR1
WDS
PX1
EX1
TR2
OV
IT1
0
0
0
0
0
0
0
1
0
0
1
1
0
1
0
1
88H
F9H
F1H
E9H
E1H
D9H
D1H
C9H
C1H
B9H
B1H
A9H
A1H
99H
91H
89H
81H
SPR1
CNT2
T2EX
I2CTX
IT0
WDE
PT0
TXD
ET0
IE0
T1
FI
0
0
0 F0H
0 E8H
0 E0H
0 D8H
0
0
0
0
1
0
1 A0H
0
1
0
1 80H
F8H
D0H
C8H
C0H
B8H
B0H
A8H
98H
90H
88H
WDWR
CAP2
PX0
RXD
EX0
SPR0
I2CI
IT0
R1
T2
P
88H
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
TCON
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
00H
MNEMONIC
RESET DEFAULT VALUE
SFR ADDRESS
F8H
F0H
E8H
E0H
D8H
D0H
C8H
C0H
B8H
B0H
A8H
A0H
98H
90H
88H
80H
ADCSTAT
–16–
WDCON
SPICON
I2CCON
T2CON
SCON
TCON
PSW
ACC
P3
P2
P1
P0
IP
IE
B
FFH
00H
00H
00H
00H
00H
10H
00H
00H
FFH
00H
FFH
00H
FFH
04H
00H
implemented; i.e., no register exists at this location. If an unoccu-
pied location is read, an unspecified value is returned. SFR locations
that are reserved for future use are shaded (RESERVED) and
should not be accessed by user software.
RESERVED
RESERVED RESERVED
RESERVED
RESERVED
RESERVED
B1H
E9H
E1H
D9H
ADCMODE
D1H
B9H
A9H
A1H
99H
89H
81H
TIMECON
PWM0L
ADC0L
ECON
TMOD
GN0L
SBUF
OF0L
IEIP2
SP
00H
55H
00H
00H
00H
00H
A0H
00H
00H
00H
07H
1
RESERVED
RESERVED
RESERVED RESERVED
RESERVED
RESERVED RESERVED
DAH
CAH
B2H
EAH
E2H
D2H
C2H
A2H
8AH
ADC0CON
82H
HTHSEC
PWM0H
RCAP2L
ADC0M
CHIPID
GN0M
OF0M
DPL
TL0
2 H
00H
55H
00H
00H
07H
00H
00H
00H
00H
1
2
RESERVED
RESERVED
RESERVED
FBH
EBH
E3H
DBH
D3H
CBH
B3H
A3H
8BH
NOT USED
ADC1CON
83H
RCAP2H
PWM1L
ADC0H
DACL
GN0H
OF0H
SEC
DPH
TL1
00H
53H
80H
00H
00H
00H
00H
00H
00H
00H
2
1
RESERVED
RESERVED
RESERVED
FCH
B4H
RESERVED
ECH
E4H
DCH
D4H
CCH
BCH
A4H
8CH
NOT USED
84H
PWM1H
EDATA1
ADC1L
DACH
GN1L
OF1L
MIN
DPP
TL2
TH0
SF
00H
9AH
00H
00H
00H
45H
00H
00H
2
00H
00H
00H
1
RESERVED
RESERVED
RESERVED
RESERVED
FDH
EDH
DDH
CDH
BDH
RESERVED
RESERVED
9DH
E5H
D5H
A5H
8DH
DACCON
EDATA2
ADC1H
HOUR
GN1H
OF1H
ICON
T3FD
TH2
TH1
00H
59H
80H
00H
00H
00H
00H
00H
00H
00H
1
2
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED RESERVED
RESERVED
RESERVED RESERVED
RESERVED
AEH
BEH
9EH
C6H
PWMCON
A6H
EDATA3
INTVAL
T3CON
EADRL
00H
00H
00H
00H
00H
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
F7H
DFH
D7H
C7H
BFH
B7H
AFH
A7H
87H
PSMCON
PLLCON
EDATA4
CFG834
DPCON
SPIDAT
EADRH
REV. A
PCON
SPH
DEH
00H
03H
00H
00H
00H
00H
00H
00H