ADUC834 Analog Devices, ADUC834 Datasheet - Page 20

• Manufacturer Part Number: ADUC834
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 62kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC834

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 4
• Other: PWM

ADuC834
ADC0H/ADC0M/ADC0L (Primary ADC Conversion Result Registers)
These three 8-bit registers hold the 24-bit conversion result from the primary ADC.
SFR Address
Power-On Default Value
Bit Addressable
ADC1H/ADC1L (Auxiliary ADC Conversion Result Registers)
These two 8-bit registers hold the 16-bit conversion result from the auxiliary ADC.
SFR Address
Power-On Default Value
Bit Addressable
OF0H/OF0M/OF0L (Primary ADC Offset Calibration Registers*)
These three 8-bit registers hold the 24-bit offset calibration coefficient for the primary ADC. These registers are configured at power-on
with a factory default value of 800000H. However, these bytes will be automatically overwritten if an internal or system zero-scale
calibration of the primary ADC is initiated by the user via MD2–0 bits in the ADCMODE Register.
SFR Address
Power-On Default Value
Bit Addressable
OF1H/OF1L (Auxiliary ADC Offset Calibration Registers*)
These two 8-bit registers hold the 16-bit offset calibration coefficient for the auxiliary ADC. These registers are configured at power-on
with a factory default value of 8000H. However, these bytes will be automatically overwritten if an internal or system zero-scale cali-
bration of the auxiliary ADC is initiated by the user via the MD2–0 bits in the ADCMODE Register.
SFR Address
Power-On Default Value
Bit Addressable
GN0H/GN0M/GN0L (Primary ADC Gain Calibration Registers*)
These three 8-bit registers hold the 24-bit gain calibration coefficient for the primary ADC. These registers are configured at power-on
with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these
bytes will be automatically overwritten if an internal or system full-scale calibration of the primary ADC is initiated by the user via
MD2–0 bits in the ADCMODE Register.
SFR Address
Power-On Default Value
Bit Addressable
GN1H/GN1L (Auxiliary ADC Gain Calibration Registers*)
These two 8-bit registers hold the 16-bit gain calibration coefficient for the auxiliary ADC. These registers are configured at power-on
with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these
bytes will be automatically overwritten if an internal or system full-scale calibration of the auxiliary ADC is initiated by the user via
MD2–0 bits in the ADCMODE Register.
SFR Address
Power-On Default Value
Bit Addressable
*These registers can be overwritten by user software only if Mode bits MD0–2 (ADCMODE SFR) are zero.
ADC0H
ADC0M
ADC0L
00H
No
ADC1H
ADC1L
00H
No
OF0H
OF0M
OF0L
800000H
No
OF1H
OF1L
8000H
No
GN0H
GN0M
GN0L
No
GN1H
GN1L
No
High Data Byte
Middle Data Byte
Low Data Byte
ADC0H, ADC0M, ADC0L
ADC0H, ADC0M, ADC0L
High Data Byte
Low Data Byte
ADC1H, ADC1L
ADC1H, ADC1L
Primary ADC Offset Coefficient High Byte
Primary ADC Offset Coefficient Middle Byte
Primary ADC Offset Coefficient Low Byte
OF0H, OF0M, OF0L, respectively
OF0H, OF0M, OF0L
Auxiliary ADC Offset Coefficient High Byte
Auxiliary ADC Offset Coefficient Low Byte
OF1H and OF1L, respectively
OF1H, OF1L
Primary ADC Gain Coefficient High Byte
Primary ADC Gain Coefficient Middle Byte
Primary ADC Gain Coefficient Low Byte
Configured at Factory Final Test; see Notes above.
GN0H, GN0M, GN0L
Auxiliary ADC Gain Coefficient High Byte
Auxiliary ADC Gain Coefficient Low Byte
Configured at Factory Final Test; see Notes above.
GN1H, GN1L
–20–
DBH
DAH
D9H
DDH
DCH
E3H
E2H
E1H
E5H
E4H
EBH
EAH
E9H
EDH
ECH
REV. A