ADP1879 Analog Devices, ADP1879 Datasheet
ADP1879
Related parts for ADP1879
ADP1879 Summary of contents
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... ADP1879 Power Saving Mode (PSM) section for more information). Available in three frequency options (300 kHz, 600 kHz, and 1 ...
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... On-Board Low Dropout (LDO) Regulator ............................. 18 Thermal Shutdown ..................................................................... 19 Programming Resistor (RES) Detect Circuit .......................... 19 Valley Current-Limit Setting .................................................... 19 Hiccup Mode During Short Circuit ......................................... 21 Synchronous Rectifier ................................................................ 21 ADP1879 Power Saving Mode (PSM) ...................................... 21 Timer Operation ......................................................................... 22 REVISION HISTORY 7/11—Revision 0: Initial Version Pseudo Fixed Frequency............................................................ 22 Power-Good Monitoring ........................................................... 23 Applications Information .............................................................. 24 Feedback Resistor Divider ...
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... Rising VIN (see Figure 35 for temperature variation) Falling VIN from operational state Do not load VREG externally because it is intended to bias internal circuitry only C = 4.7 µF to PGND, 0.22 µF to GND, V VREG ADP1878ARQZ-0.3-R7/ADP1879ARQZ-0.3-R7 (300 kHz) ADP1878ARQZ-0.6-R7/ADP1879ARQZ-0.6-R7 (600 kHz) ADP1878ARQZ-1.0-R7/ADP1879ARQZ-1.0-R7 (1.0 MHz 100 100 mA IN ...
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... ADP1878/ADP1879 Parameter Symbol ADP1878ARQZ-0.6-R7/ ADP1879ARQZ-0.6-R7 On Time Minimum On Time Minimum Off Time ADP1878ARQZ-1.0-R7/ ADP1879ARQZ-1.0-R7 On Time Minimum On Time Minimum Off Time OUTPUT DRIVER CHARACTERISTICS High-Side Driver Output Source Resistance Output Sink Resistance Rise Time DRVH 2 Fall Time t f, DRVH Low-Side Driver Output Source Resistance ...
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... V to (VREG + 0.3 V) Package Type −0 +28 V θ (14-Lead LFCSP_WD) −0 VREG JA 4-Layer Board ±0 ESD CAUTION 30°C/W −40°C to +125°C −65°C to +150°C JEDEC J-STD-020 300°C Rev Page ADP1878/ADP1879 θ Unit JA 30 °C/W ...
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... EN 12 DRVH PGND GND 10 DRVL 5 RES PGOOD 6 9 VREG TOP VIEW (Not to Scale) NOTES 1. CONNECT THE EXPOSED PAD TO THE ANALOG GROUND PIN (GND). Figure 3. Pin Configuration ADP1878/ADP1879 Controller (Includes the Output Gate Drivers). Rev Page Data Sheet ...
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... INFINEON FETs: 5 BSC042N03MS G (UPPER/LOWER 100 1k LOAD CURRENT (mA) Figure 6. Efficiency—300 kHz 16.5V IN 10k 100k = 0.8 V OUT 10k 100k = 1.8 V OUT 10k 100k = 7 V OUT Rev Page ADP1878/ADP1879 100 13V 13V (PSM 16. 25°C ...
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... ADP1878/ADP1879 100 13V 13V (PSM 25° 0.8V OUT V = 16.5V (PSM 1.0MHz SW 20 WÜRTH INDUCTOR: 15 744303012 0.12µH, DCR = 0.33mΩ 10 INFINEON FETs: 5 BSC042N03MS G (UPPER/LOWER 100 1k LOAD CURRENT (mA) Figure 10. Efficiency—1.0 MHz, V 100 ...
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... V OUT = 5 V OUT Rev Page ADP1878/ADP1879 V = 13V V = 16. +125°C +125°C +25°C +25°C –40°C –40°C 0 2000 4000 6000 8000 LOAD CURRENT (mA) Figure 19. Output Voltage Accuracy— ...
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... ADP1878/ADP1879 601.0 600 5V 20V REG IN 600.0 599 5V 13V REG IN 599.0 598.5 598.0 597.5 597.0 –40.0 –7.5 25.0 57.5 TEMPERATURE (°C) Figure 22. Feedback Voltage vs. Temperature 325 +125°C +25°C –40°C 315 305 295 285 275 265 255 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 V (V) IN Figure 23. Switching Frequency vs. High Input Voltage, 300 kHz, ±10 650 +125° ...
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... V OUT 1225 1150 1075 1000 925 850 775 700 +125°C 625 +25°C –40°C 550 = 1.8 V OUT Rev Page ADP1878/ADP1879 740 V = 13V +125°C IN 733 +25° 16.5V IN 726 –40°C 719 712 705 698 691 684 677 ...
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... ADP1878/ADP1879 1450 V = 13V +125°C IN +25° 16.5V IN 1400 –40°C 1350 1300 1250 1200 1150 1100 1050 1000 0 800 1600 2400 3200 4000 4800 5600 6400 7200 LOAD CURRENT (mA) Figure 34. Frequency vs. Load Current, 1.0 MHz, V 2.658 2.657 2.656 2.655 2.654 2.653 2 ...
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... Figure 43. Low-Side MOSFET Body Diode Conduction Time vs 25° 4.7 5.1 5.5 Figure 44. Power Saving Mode (PSM) Operational Waveform, 100 4.7 5.1 5.5 REG Rev Page ADP1878/ADP1879 300kHz 1MHz 8 2.7 3.1 3.5 3.9 4.3 4.7 V (V) REG OUTPUT VOLTAGE INDUCTOR CURRENT SW NODE LOW SIDE CH2 5A Ω B CH1 50mV M400ns ...
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... ADP1878/ADP1879 OUTPUT VOLTAGE 4 INDUCTOR CURRENT 1 SW NODE 3 CH1 5A Ω M400ns B CH3 10V CH4 100mV T 30.6% W Figure 46. CCM Operation at Heavy Load (See Figure 95 for Application Circuit) OUTPUT VOLTAGE 2 12A STEP CH1 10A Ω B CH2 200mV M2ms W T 75.6% CH3 20V CH4 5V Figure 47. Load Transient Step— ...
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... Figure 55. Start-Up Behavior at Heavy Load 300 kHz CH1 920mV CH2 8.20A Figure 57. Output Voltage Ripple Waveform During PSM Operation Rev Page ADP1878/ADP1879 OUTPUT VOLTAGE INDUCTOR CURRENT LOW SIDE SW NODE CH2 5A Ω B CH1 2V M2ms A CH1 W CH3 10V CH4 5V T 32.8% ...
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... ADP1878/ADP1879 T = 25°C LOW SIDE MINUS SW CH2 5V M40ns CH3 5V CH4 2V T 29.0% MATH 2V 40ns Figure 58. Output Drivers and SW Node Waveforms t LOW SIDE 16ns ( f ,DRVL t 22ns ( ) 4 pdh DRVH 25ns ( SW NODE MINUS M SW CH2 5V M40ns T 29.0% CH3 5V CH4 2V MATH 2V 40ns Figure 59. High-Side Driver Rising and Low-Side Falling Edge Waveforms (C 4 ...
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... This allows the to drive all N-channel power stages to regulate output voltages to as low as 0.6 V. Rev Page ADP1878/ADP1879 PGOOD FB VREG VIN (TRIMMED 2RC OUT IN SW FILTER BST DRVH 300kΩ LEVEL HS SW SHIFT 8kΩ VREG LS DRVL 800kΩ PGND 0.4V ADP1878/ADP1879 ...
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... PRECISION ENABLE CIRCUITRY The ADP1878/ADP1879 have precision enable circuitry. The precision enable threshold is 630 mV including hysteresis (see Figure 66). Connecting the EN pin to GND disables the ADP1878/ADP1879, reducing the supply current of the device to approximately 140 µA. V REG 10kΩ EN Figure 66. Connecting EN Pin to VREG via a Pull-Up Resistor to Enable the ...
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... CS GAIN 0.4V SET RES V/V 6 V/V 12 V/V 24 V/V ADP1878/ADP1879 is based on valley of the low-side MOSFET, the output voltage ON of the low-side MOSFET ON ADP1878/ADP1879 are based on valley current and I is CLIM LOAD 1 2 helps to determine the inductor value (see the I = 0.33 LOAD RIPPLE CURRENT = 3 LOAD CURRENT ...
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... MOSFET the current sense gain multiplier (see Table 6 and Table 7). CS Although the ADP1878/ADP1879 have only four discrete current sense gain settings for a given R variable, Table 7 and Figure 71 ON outline several available options for the valley current setpoint based on various R values ...
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... MOSFETs or reduce efficiency because of excessive power loss. ADP1879 POWER SAVING MODE (PSM) A power saving mode is provided in the ADP1879. The operates in the discontinuous conduction mode (DCM) and pulse skips at light to medium load currents. The controller outputs pulses as necessary to maintain output regulation ...
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... For typical applications where V not relevant; however, for lower V PSEUDO FIXED FREQUENCY timer, senses ON The ADP1878/ADP1879 ) OUT scheme. During steady state operation, the switching frequency stays relatively constant, or pseudo fixed. This is due to the one shot t fixed duration, given that external conditions such as input voltage, output voltage, and load current are also at steady state ...
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... R is the PGOOD external resistor. PGD user chosen voltage rail. EXT VALLEY TRIP POINTS PGOOD Figure 80. Power-Good Timing Diagram, t Rev Page ADP1878/ADP1879 140 PGOOD 690mV 140mV – FB 600mV 530mV Figure 79. Power Good, Output Voltage Monitoring Circuit OUTPUT OVERVOLTAGE ...
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... ADP1878/ADP1879 APPLICATIONS INFORMATION FEEDBACK RESISTOR DIVIDER The required resistor divider network can be determined for a given V value because the internal band gap reference (V OUT is fixed at 0.6 V. Selecting values for R T minimum output load current of the converter. Therefore, for a given value the R ...
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... V/V: The relationship between C follows: The zero frequency is set to 1/4 Combining all of the above parameters results in where ESR is the equivalent series resistance of the output capacitors. Rev Page ADP1878/ADP1879 COMP is significantly smaller than the zero frequency, is set to be 1/4 ZERO ...
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... The ratio of this time constant to the period of one switching cycle is the multiplying factor to be used in the following expression Body Diode Conduction Loss The ADP1878/ADP1879 that prevents the high- and low-side MOSFETs from conducting )] + [V × current simultaneously. This overlap control is beneficial, avoiding BIAS REG large current flow that may lead to irreparable damage to the external components of the power stage ...
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... LDO, the ac current (fxCxV) consumed by the internal drivers to drive the external MOSFETs, adds another element of Rev Page ADP1878/ADP1879 , , = × ESR) RIPP LOAD,MAX is the maximum load current. into the charge balance equation to MAX,RIPPLE are used for dc-to-dc, step down, high ADP1878/ADP1879 employ an ...
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... LDO. Equation 3 shows the power dissipation calculations for the integrated drivers and for the internal LDO. Table 9 lists the thermal impedance for the ADP1878/ADP1879, which are available in a 14-lead LFCSP_WD. Table 9. Thermal Impedance for 14-Lead LFCSP_WD Package Thermal Impedance 14-Lead LFCSP_WD θ ...
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... Choose five 270 μF polymer capacitors. The rms current through the output capacitor is The power loss dissipated through the ESR of the output capacitor is P COUT Rev Page ADP1878/ADP1879 of 4.5 mΩ and the ON = 100 kΩ for a current RES ADP1878 = 0.05 × 1 DROOP ∆ ...
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... ADP1878/ADP1879 Feedback Resistor Network Setup Choosing kΩ example. Calculate R B 1 kΩ 2 kΩ 0.6 V Compensation Network To calculate and C , the transconductance COMP COMP PAR parameter and the current sense gain variable are required. The transconductance parameter ( 500 μA/V, and the current ...
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... Rev Page ADP1878/ADP1879 = 1kΩ 5.4 mΩ (BSC042N03MS G), BOT COMP PAR (μH) (kΩ) (pF) (pF) 0.72 56.9 620 62 1.0 56.9 620 62 1.2 56.9 470 47 1 ...
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... ADP1878/ADP1879 Table 11. Recommended Inductors L (µH) DCR (mΩ) I SAT 0.12 0.33 55 0.22 0.33 30 0.47 0.8 50 0.72 1.65 35 0.9 1.6 32 1.2 1.8 25 1.0 3.8 16 1.4 3.2 24 2.0 2.6 23 0.8 27.5 Table 12. Recommended MOSFETs (mΩ High-Side MOSFET 5.4 47 (Q1/Q2) 10 Low-Side MOSFET 5.4 47 (Q3/Q4) 10.2 82 6.0 19 (A) Dimension (mm) 10.2 × 7 10.2 × 7 14.2 × 12.8 10.5 × 10.2 14 × 12.8 10.5 × 10.2 10.2 × 10.2 14 × 12.8 10.2 × 10.2 (A) V (V) C (nF) ...
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... SEPARATE ANALOG GROUND PLANE FOR COMPENSATION AND FEEDBACK RESISTORS Figure 87. Overall Layout of the ADP1878/ADP1879 High Current Evaluation Board Figure 86 shows the schematic of a typical used for a high current application. Blue traces denote high current pathways. VIN, PGND, and V possibly replicated, descending down into the multiple layers. ...
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... ADP1878/ADP1879 TOP RESISTOR FEEDBACK TAP VOUT SENSE TAP LINE EXTENDING BACK TO THE TOP RESISTOR IN THE FEEDBACK DIVIDER NETWORK. THIS OVERLAPS WITH PGND SENSE TAP LINE EXTENDING TO THE ANALOG GROUND PLANE Figure 88. Layer 2 of Evaluation Board Figure 89. Layer 3 of Evaluation Board Rev Page ...
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... Ensure that the negative terminals of the output capacitors are placed close to the main power ground (PGND), as previously mentioned. All of these points form a tight circle (component geometry permitting) that minimizes the area of flux change as the event switches between D and 1 − D. Rev Page ADP1878/ADP1879 ) is at the rightmost end of OUT ...
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... Figure 91. Primary Current Pathways During the On State of the High-Side MOSFET (Left Arrow) and the On State of the Low-Side MOSFET (Right Arrow) DIFFERENTIAL SENSING Because the ADP1878/ADP1879 operate in valley current-mode control, a differential voltage reading is taken across the drain and source of the low-side MOSFET. Connect the drain of the low-side MOSFET s as close as possible to the SW pin (Pin 13) of the IC ...
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... X7R, 1210 GRM32ER71E226KE15L PANASONIC: (OUTPUT CAPACITORS) 34nF 180µF (SP-SERIES), 4V, 10mΩ, EEFUE0G181XR INFINEON MOSFETs: BSC042N03MS G (LOWER SIDE) BSC080N03MS G (UPPER SIDE) WÜRTH INDUCTORS: 0.47µH, 0.8mΩ, 30A, 744355147 Rev Page ADP1878/ADP1879 22µF 22µF 22µF N/A N 1.8V, 12A ...
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... RES 100kΩ VREG 0.1µF 1µF Figure 95. Application Circuit for 13 V Input, 1.8 V Output 300 kHz (Q2/Q4 No Connect) HIGH VOLTAGE INPUT V = 13V IN C3 22µF 22µF ADP1878/ C BST ADP1879 100nF BST 1.2µH DRVH 12 R SNB 2Ω PGND 11 C SNB 1 ...
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... END VIEW 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.15 REF 0.50 BSC COMPLIANT TO JEDEC STANDARDS MO-229-WEGD Figure 96. 14-Lead Lead Frame Chip Scale Package [LFCSP_WD × Body, Very Very Thin Dual (CP-14-2) Dimensions shown in millimeters Rev Page ADP1878/ADP1879 3.40 3.30 3.15 0.20 MIN 8 14 1.80 EXPOSED PAD 1.70 1. BOTTOM VIEW ...
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... ADP1879ACPZ-0.6-R7 −40°C to +125°C ADP1879ACPZ-1.0-R7 −40°C to +125°C ADP1879-0.3-EVALZ ADP1879-0.6-EVALZ ADP1879-1.0-EVALZ RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...