ADP1879 Analog Devices, ADP1879 Datasheet - Page 28

• Manufacturer Part Number: ADP1879
• Description: Synchronous Buck Controller with Constant On-Time and Valley Current Mode with Power Saving Mode
• Manufacturer: Analog Devices

ADP1878/ADP1879
power dissipation across the internal LDO. Equation 3 shows the
power dissipation calculations for the integrated drivers and for
the internal LDO. Table 9 lists the thermal impedance for the
ADP1878/ADP1879, which are available in a 14-lead LFCSP_WD.
Table 9. Thermal Impedance for 14-Lead LFCSP_WD
Package
14-Lead LFCSP_WD θ
Figure 85 specifies the maximum allowable ambient temperature
that can surround the
high input voltage (V
derating conditions for each available switching frequency for
low, typical, and high output setpoints for the 14-lead LFCSP_WD
package. All temperature derating criteria are based on a
maximum IC junction temperature of 125°C.
The maximum junction temperature allowed for the ADP1878/
ADP1879
temperature (T
caused by the thermal impedance of the package and the internal
power dissipation, should not exceed 125°C, as dictated by the
following expression:
where:
T
T
dissipated from within.
T
J
R
A
4-Layer Board
is the maximum junction temperature.
is the rise in package temperature due to the power
is the ambient temperature.
T
4-Layer Evaluation Board, C
J
= T
130
120
110
100
90
IC is 125°C. This means that the sum of the ambient
5.5
R
× T
A
7.0
) and the rise in package temperature (T
Figure 85. Ambient Temperature vs. V
A
300kHz
600kHz
1MHz
8.5
JA
IN
ADP1878/ADP1879
). Figure 85 illustrates the temperature
10.0
IN
11.5
= 4.3 nF (High-/Low-Side MOSFET)
V
V
V
OUT
OUT
OUT
V
Thermal Impedance
30°C/W
IN
13.0
= 0.8V
= 1.8V
= HIGH SETPOINT
(V)
14.5
IC for a specified
16.0
IN
,
17.5
R
), which is
19.0
Rev. 0 | Page 28 of 40
(1)
The rise in package temperature is directly proportional to its
thermal impedance characteristics. The following equation
represents this proportionality relationship:
where:
θ
the outside surface of the die, where it meets the surrounding air.
P
The bulk of the power dissipated is due to the gate capacitance of
the external MOSFETs and current running through the on-board
LDO. The power loss equations for the MOSFET drivers and
internal low dropout regulator (see the MOSFET Driver Loss
section and the Efficiency Consideration section) are:
where:
C
C
I
side drivers.
V
the rectifier drop (see Figure 83)).
V
where P
in the LDO block across V
P
V
V
C
I
For example, if the external MOSFET characteristics are θ
(14-lead LFCSP_WD) = 30°C/W, f
C
then the power loss is
BIAS
BIAS
JA
DR(LOSS)
DR(LOSS)
upperFET
lowerFET
TOTAL
upperFET
DR
REG
IN
REG
is the thermal resistance of the package from the junction to
is the high voltage input.
is the driver bias voltage (the low input voltage (V
is the dc current (2 mA) flowing into the high- and low-
is the dc input bias current.
T
P
[V
P
V
P
[V
= (4.62 × (300 × 10
(5.0 × (300 × 10
= 57.12 mW
P
(13 V – 5 V) × (300 × 10
= 55.6 mW
P
= 77.13 mW + 55.6 mW
= 132.73 mW
is the LDO output/bias voltage.
is the LDO output voltage and bias voltage.
DR(LOSS)
DISS(LDO)
DR(LOSS)
DISS(LDO)
DISS(TOTAL)
R
REG
is the C
REG
REG
= θ
is the input gate capacitance of the low-side MOSFET.
= 3.3 nF, C
is the input gate capacitance of the high-side MOSFET.
is the overall power dissipated by the IC.
DISS(LDO)
is the MOSFET driver loss.
+ I
× (f
× (f
JA
BIAS
= [V
= [V
× P
= P
= (V
SW
GD
SWClowerFET
= P
is the power dissipated through the pass device
C
DR(LOSS)
DR(LOSS)
+ C
DR
DR
lowerFET
lowerFET
IN
DISS(LDO)
× (f
× (f
– V
GS
3
× 3.3 × 10
V
of the external MOSFET.
SW
SWCupperFET
+ (V
= 3.3 nF, V
REG
V
3
REG
× 3.3 × 10
C
REG
+ P
) × (f
IN
upperFET
+ I
IN
and V
+ I
DR(LOSS)
3
– V
BIAS
× 3.3 × 10
SW
BIAS
−9
V
V
SW
)]
REG
DR
DR
× C
× 5.0 + 0.002))
DR
REG
)]
−9
= 300 kHz, I
) × (f
= 4.62 V, and V
+ I
+ I
.
× 4.62 + 0.002)) +
TOTAL
BIAS
BIAS
−9
SW
)] +
× V
)] +
× 5 + 0.002)
× C
REG
Data Sheet
BIAS
TOTAL
+ I
= 2 mA,
REG
REG
BIAS
×
) minus
= 5.0 V,
) =
JA
(2)
(3)
(4)