ADP1879 Analog Devices, ADP1879 Datasheet - Page 6

• Manufacturer Part Number: ADP1879
• Description: Synchronous Buck Controller with Constant On-Time and Valley Current Mode with Power Saving Mode
• Manufacturer: Analog Devices

ADP1878/ADP1879
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
VIN
COMP
EN
FB
GND
RES
VREG
SS
PGOOD
DRVL
PGND
DRVH
SW
BST
EP
Description
High-Side Input Voltage. Connect VIN to the drain of the high-side MOSFET.
Output of the Error Amplifier. Connect compensation network between this pin and AGND to achieve stability (see
the Compensation Network section).
IC Enable. Connect EN to VREG to enable the IC. When pulled down to AGND externally, EN disables the IC.
Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.
Analog Ground Reference Pin of the IC. Connect all sensitive analog components to this ground plane (see the Layout
Considerations section).
Current Sense Gain Resistor (External). Connect a resistor between the RES pin and GND (Pin 5).
Internal Regulator Supply Bias Voltage for the
Connecting a bypass capacitor of 1 µF directly from this pin to PGND and a 0.1 µF capacitor across VREG and GND are
recommended.
Soft Start Input. Connect an external capacitor to GND to program the soft start period. There is a capacitance value
of 10 nF for every 1 ms of soft start delay.
Open-Drain Power-Good Output. PGOOD sinks current when FB is out of regulation or during thermal shutdown.
Connect a 3 kΩ resistor between PGOOD and VREG. Leave PGOOD unconnected if it is not used.
Drive Output for the External Low-Side, N-Channel MOSFET. This pin also serves as the current sense gain setting pin
(see Figure 69).
Power Ground. Ground for the low-side gate driver and low-side N-channel MOSFET.
Drive Output for the External High-Side N-Channel MOSFET.
Switch Node Connection.
Bootstrap for the High-Side N-Channel MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected
between VREG and BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected
between VREG and BST for increased gate drive capability.
Exposed Pad. Connect the exposed pad to the analog ground pin (GND).
NOTES
1. CONNECT THE EXPOSED PAD TO THE
COMP
VREG
GND
RES
ANALOG GROUND PIN (GND).
VIN
EN
FB
ADP1878/ADP1879
1
2
3
4
5
6
7
Figure 3. Pin Configuration
(Not to Scale)
Rev. 0 | Page 6 of 40
TOP VIEW
ADP1878/ADP1879
14
13
12
10
11
9
8
BST
SW
DRVH
PGND
DRVL
PGOOD
SS
Controller (Includes the Output Gate Drivers).
Data Sheet