ADP1879 Analog Devices, ADP1879 Datasheet - Page 23

• Manufacturer Part Number: ADP1879
• Description: Synchronous Buck Controller with Constant On-Time and Valley Current Mode with Power Saving Mode
• Manufacturer: Analog Devices

Data Sheet
is sensed through the counter action upswing of the output
(COMP) of the error amplifier.
The result is a convergence of these two signals (see Figure 78),
which allows an instantaneous increase in switching frequency
during the positive load transient event. In summary, a positive
load step causes V
transient up and, therefore, shortens the off time. This resulting
increase in frequency during a positive load transient helps to
quickly bring V
window.
Similarly, a negative load step causes the off time to lengthen in
response to V
demagnetizing phase, helping to bring V
In this case, the switching frequency decreases, or experiences a
foldback, to help facilitate output voltage recovery.
Because the
to sudden changes in load demand, the recovery period in which
the output voltage settles back to its original steady state operating
point is much quicker than it would be for a fixed frequency
equivalent. Therefore, using a pseudo fixed frequency results in
significantly better load transient performance compared to
using a fixed frequency.
POWER-GOOD MONITORING
The
output voltage via the FB pin. The PGOOD pin is an open-
drain output that can be pulled up by an external resistor to a
voltage rail that does not necessarily have to be VREG. When
the internal NMOS switch is in high impedance (off state), this
means that the PGOOD pin is logic high and the output voltage
via the FB pin is within the specified regulation window. When
ADP1878/ADP1879
PWM OUTPUT
ADP1878/ADP1879
ERROR AMP
OUTPUT
CS AMP
Figure 78. Load Transient Response Operation
OUTPUT
OUT
LOAD CURRENT
OUT
DEMAND
rising. This effectively increases the inductor
OUT
back up in value and within the regulation
to transient down, which causes COMP to
f
SW
power-good circuitry monitors the
have the ability to respond rapidly
>
f
SW
OUT
VALLEY
TRIP POINTS
within regulation.
Rev. 0 | Page 23 of 40
the internal switch is turned on, PGOOD is internally pulled low
when the output voltage via the FB pin is outside this regulation
window.
The power-good window is defined with a typical upper speci-
fication of +90 mV and a lower specification of −70 mV below
the FB voltage of 600 mV. When an overvoltage event occurs at the
output, there is a typical propagation delay of 12 μs prior to the
deassertion (logic low) of the PGOOD pin. When the output
voltage reenters the regulation window, there is a propagation
delay of 12 μs prior to PGOOD reasserting back to a logic high
state. When the output is outside the regulation window, the
PGOOD open-drain switch is capable of sinking 1 mA of
current and providing 140 mV of drop across this switch. The
user is free to tie the external pull-up resistor (R
voltage rail up to 20 V. The following equation provides the
proper external pull-up resistor value:
where:
R
V
PGD
EXT
Figure 80. Power-Good Timing Diagram, t
PGOOD
is a user chosen voltage rail.
is the PGOOD external resistor.
FB
Figure 79. Power Good, Output Voltage Monitoring Circuit
690mV
530mV
600mV
0V
690mV
640mV
600mV
530mV
FB
SOFT START
V EXT
0V
Disproportionate For Illustration Purposes)
1 mA
HYSTERESIS (50mV)
140 mV
t
PGD
PGOOD
ASSERTION
AT POWER-UP
t
PGD
ADP1878/ADP1879
PGD
+
140mV
–
OUTPUT OVERVOLTAGE
PGOOD DEASSERT
AT POWER-DOWN
= 12 μs (Diagram May Look
PGOOD
REASSERT
DEASSERTION
t
PGD
PGOOD
t
PGOOD
PGD
1mA
RES
V
) to any
EXT
R
PGD