LPC2939 NXP Semiconductors, LPC2939 Datasheet

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... ADCs, and multiple serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, and communication markets. To optimize system power consumption, the LPC2939 has a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling. 2. Features and benefits  ...

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... I/O operating voltage: 2 3.6 V; inputs tolerant up to 5.5 V  208-pin LQFP package LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 © NXP B.V. 2010. All rights reserved ...

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... UART Host/ RS-485/ OTG/ modem device 32-bit yes 2 2  TCM All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Version SOT459-1 LIN 2.0/ CAN Package UART 2 2 LQFP208 © NXP B.V. 2010. All rights reserved ...

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... CAN0/1 networking subsystem GLOBAL ACCEPTANCE FILTER UART/LIN0 C0/1 Grey-shaded blocks represent peripherals and memory regions accessible by the GPDMA. Fig 1. LPC2939 block diagram LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB JTAG interface TEST/DEBUG INTERFACE ITCM DTCM 8 kB SRAM ...

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... Pin description 5.2.1 General description The LPC2939 uses five ports: port 0 and port 1 with 32 pins, ports 2 with 28 pins each, port 3 with 16 pins, port 4 with 24 pins, and port 5 with 20 pins. The pin to which each function is assigned is controlled by the SFSP registers in the SCU. The functions combined on each port pin are shown in the pin description tables in this section ...

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... SPI2 SDO TIMER1 CAP0/ ADC0 EXTSTART EXTBUS CS6 TIMER1 CAP1/ ADC1 EXTSTART TIMER0 CAP2 All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Function 2 Function 3 PWM3 CAP0 EXTBUS D21 PWM1 MAT0 LIN1/UART TXD PWM1 MAT1 LIN1/UART RXD ...

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... TIMER3 CAP2 TIMER3 CAP1 TIMER3 CAP0 TIMER2 CAP3 EXTBUS A12 TIMER2 CAP2 EXTBUS D16 TIMER2 MAT0 All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Function 2 Function 3 UART1 DSR - TIMER0 MAT3 EXTINT7 UART0 OUT2 - PWM TRAP2 PWM3 MAT3 ...

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... TIMER2 CAP0 USB_OVRCR2 EXTINT3 EXTBUS A13 EXTINT2 EXTBUS D17 TIMER2 MAT2 TIMER2 MAT3 SPI1 SCK SPI1 SDI SPI1 SCS0 SPI1 SDO All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Function 2 Function PWM TRAP2 EXTBUS PWM1 MAT4 USB_PWRD1 - ...

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... SPI1 SDI SPI1 SCK CLK_OUT USB_UP_LED1 SPI2 SCS1 SPI2 SCS3 EXTINT1 All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Function 2 Function 3 EXTINT0 EXTBUS D12 EXTINT1 EXTBUS D13 LIN1 RXD/UART RXD EXTBUS CS1 LIN1 TXD/ UART TXD EXTBUS CS0 ...

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... ADC0 IN7 EXTBUS D22 ADC0 IN4 USB_PPWR2 ADC0 IN5 EXTBUS A20 ADC0 IN0 All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Function 2 Function 3 PWM3 MAT0 EXTBUS A0 PWM0 MAT2 SPI0 SCS0 PWM0 MAT3 SPI0 SCK CAN0 TXD ...

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... I C1 SDA SCL TIMER3 MAT0 EXTBUS A11 TIMER3 MAT1 EXTBUS D11 ADC1 IN4 USB_CONNECT2 All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Function 2 Function 3 UART0 PWM0 MAT3 EXTBUS D29 UART0 RTS - PWM0 MAT4 EXTBUS D30 ...

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... UART1 RXD ADC2 IN2 ADC2 IN3 TIMER3 MAT2 TIMER3 MAT3 SPI2 SCS1 SPI2 SCS0 All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Function 2 Function 3 PWM1 MAT3 EXTBUS A11 UART0 CTS - PWM1 MAT4 EXTBUS A12 UART0 DCD ...

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... Function 1 ADC2 IN4 ADC2 IN5 ADC2 IN6 ADC2 IN7 SPI2 SDO All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Function 2 Function 3 PWM2 MAT2 EXTBUS A16 PWM2 MAT3 EXTBUS A17 PWM2 MAT4 EXTBUS A18 PWM2 MAT5 ...

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... One ARM Peripheral Bus for event router and system control The LPC2939 configures the ARM968E-S processor in little-endian byte order. All peripherals run at their own clock frequency to optimize the total system power consumption. The AHB-to-APB bridge used in the subsystems contains a write-ahead buffer one transaction deep ...

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... The ARM968E-S processor is described in detail in the ARM968E-S data sheet 6.3 On-chip flash memory system The LPC2939 includes a 768 kB flash memory system. This memory can be used for both code and data storage. Programming of the flash memory can be accomplished via the flash memory controller or the JTAG. ...

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... ITCM/DTCM 0x0040 8000 memory 32 kB DTCM 0x0040 0000 reserved 0x0000 8000 32 kB ITCM 0x0000 0000 Fig 3. LPC2939 memory map 4 GB 0xFFFF FFFF PCR/VIC control 0xFFFF 8000 reserved 0xF080 0000 DMA interface to TCM 0xF000 0000 reserved 0xE018 3000 ETB control ...

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... LP_OSC speed is too low for the external debugging environment. 6.6.2 Reset strategy The LPC2939 contains a central module, the Reset Generator Unit (RGU) in the Power, Clock and Reset Subsystem (PCRSS), which controls all internal reset signals towards the peripheral modules. The RGU provides individual reset control as well as the monitoring functions needed for tracing a reset back to source ...

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... Clocking strategy 6.7.1 Clock architecture The LPC2939 contains several different internal clock areas. Peripherals like Timers, SPI, UART, CAN and LIN have their own individual clock sources called base clocks. All base clocks are generated by the Clock Generator Unit (CGU0). They may be unrelated in frequency and phase and can have different clock sources within the CGU ...

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... USB REGISTERS general subsytem SYSTEM CONTROL EVENT ROUTER CFID peripheral subsystem GPIO0/1/2/3/4/5 TIMER 0/1/2/3 SPI0/1/2 UART0/1 WDT Fig 4. LPC2939 overview of clock areas LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB BA SE_ICLK0_CLK BASE_ICLK1_CLK BASE_IVNSS_CLK branch clocks branch clocks BASE_PCR_CLK branch ...

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... Base clock and branch clock relationship Table 7 contains an overview of all the base blocks in the LPC2939 and their derived branch clocks. A short description is given of the hardware parts that are clocked with the individual branch clocks. In relevant cases more detailed information can be found in the specific subsystem description ...

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... CGU1 base clock and branch clock overview Branch clock name CLK_OUT_CLK CLK_USB_CLK CLK_USB_I2C_CLK All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 …continued Parts of the device clocked by this branch clock APB side of the MSCSS timer 0 in the MSCSS timer 1 in the MSCSS ...

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... LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 © NXP B.V. 2010. All rights reserved ...

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... Flash sector overview Sector size (kB All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Sector base address 0x2000 0000 0x2000 2000 0x2000 4000 0x2000 6000 0x2000 8000 © NXP B.V. 2010. All rights reserved ...

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... Section 6.6.3. All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Sector base address 0x2000 A000 0x2000 C000 0x2000 E000 0x2001 0000 0x2002 0000 0x2003 0000 0x2004 0000 0x2005 0000 0x2006 0000 0x2007 0000 ...

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... It contains one 16 kB memory block and is byte-programmable and byte-erasable. The EEPROM can be accessed only through the flash controller. 6.9 External Static Memory Controller (SMC) The LPC2939 contains an external Static Memory Controller (SMC) which provides an interface for external (off-chip) memory devices. Key features are: • ...

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... Pin description The external static-memory controller module in the LPC2939 has the following pins, which are combined with other functions on the port pins of the LPC2939. the external memory controller pins. Table 13. Symbol EXTBUS CSx EXTBUS BLSy EXTBUS WE ...

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... ARM9 microcontroller with CAN, LIN, and USB CLK(SYS WSTOEN CLK(SYS) CS (1) WE/BLS BLS A D WSTWEN All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 WST1 002aae704 Figure 6. The relationship WST2 002aae705 © NXP B.V. 2010. All rights reserved ...

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... LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB WST1 IDCY WSTOEN All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Figure 7. Extra wait states WST2 WSTWEN 002aae706 © NXP B.V. 2010. All rights reserved ...

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... The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the Host controller. The LPC2939 USB interface includes a device and OTG controller with on-chip PHY for device. The OTG switching protocol is supported through the use of an external controller. ...

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... When this function is not enabled BUS via its corresponding PINSEL register driven HIGH internally. positive differential data negative differential data All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Interfacing - - - - - external OTG transceiver external OTG transceiver ...

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... The CFID has no external pins. 6.12.3 System Control Unit (SCU) The system control unit contains system related functions.The key feature is configuration of the I/O port pins multiplexer. It defines the function of each I/O pin of the LPC2939. The I/O pin configuration should be consistent with peripheral function usage. The SCU has no external pins. ...

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... The vectored interrupt controller inputs are active HIGH. 6.12.4.1 Pin description The event router module in the LPC2939 is connected to the pins listed below. The pins are combined with other functions on the port pins of the LPC2939. pins connected to the event router and three additional internal signals. ...

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... CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_SAFE which is always on. 6.13.3 Timer The LPC2939 contains six identical timers: four in the peripheral subsystem and two in the Modulation and Sampling Control SubSystem (MSCSS) located at different peripheral base addresses. This section describes the four timers in the peripheral subsystem. Each timer has four capture inputs and/or match outputs ...

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... SubSystem. In the Modulation and Sampling SubSystem each timer also has its own individual clock source. See 6.13.3.1 Pin description The four timers in the peripheral subsystem of the LPC2939 have the pins described below. The two timers in the modulation and sampling subsystem have no external pins except for the pause pin on MSCSS timer 1. See timers and their associated pins ...

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... FIFOs, but they can also be put into 450 mode without FIFOs. Remark: The LIN controller can be configured to provide two additional standard UART interfaces (see 6.13.4.1 Pin description The UART pins are combined with other functions on the port pins of the LPC2939. Table 17 shows the UART pins (x runs from 0 to 1). Table 17. ...

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... The register interface towards the system bus is clocked by CLK_SYS_PESS. The baud generator is clocked by the CLK_UARTx. 6.13.5 Serial peripheral interface (SPI) The LPC2939 contains three Serial Peripheral Interface modules (SPIs) to allow synchronous serial communication with slave or master peripherals. The key features are: • ...

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... SPI. Each data frame is between four and 16 bits long, depending on the size of words programmed, and is transmitted starting with the MSB. 6.13.5.2 Pin description The SPI pins are combined with other functions on the port pins of the LPC2939, see Section 6.12.3. Table 18. ...

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... Pin description The six GPIO ports in the LPC2939 have the pins listed below. The GPIO pins are combined with other functions on the port pins of the LPC2939. pins. ...

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... Pin description The two CAN controllers in the LPC2939 have the pins listed below. The CAN pins are combined with other functions on the port pins of the LPC2939. pins (x runs from 0 to 1). ...

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... Note that the pins are not I 6.15 Modulation and Sampling Control SubSystem (MSCSS) The Modulation and Sampling Control Subsystem (MSCSS) in the LPC2939 includes four Pulse-Width Modulators (PWMs), three 10-bit successive approximation Analog-to-Digital Converters (ADCs) and two timers. The key features of the MSCSS are: ...

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... Note that the PWMs run on the PWM clock and the ADCs on the ADC clock, see Section 6.16.2. LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 © NXP B.V. 2010. All rights reserved ...

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... PWM3 TRAP0 PWM0 CAP[2:0] TRAP1 PWM1 CAP[2:0] TRAP2 PWM2 CAP[2:0] TRAP3 PWM3 CAP[2:0] All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 IDX0 PHA0 PHB0 ADC0 IN[7:0] ADC0 EXTSTART ADC1 IN[7:0] ADC1 EXTSTART ADC2 IN[7:0] ADC2 EXTSTART PWM0 MAT[5:0] PWM1 MAT[5:0] ...

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... NXP Semiconductors 6.15.2 Pin description The pins of the LPC2939 MSCSS associated with the three ADC modules are described in Section Section 6.15.5.4, pins directly connected to the MSCSS timer 1 module are described in Section 6.15.6.1, and pins connected to the quadrature encoder interface are described in Section 6.15.7.1. 6.15.3 Clock description The MSCSS is clocked from a number of different sources: • ...

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... ADC block diagram 6.15.4.2 Pin description The three ADC modules in the MSCSS have the pins described below. The ADCx input pins are combined with other functions on the port pins of the LPC2939. The VREFN and VREFP pins are common to all ADCs. LPC2939_3 Product data sheet ...

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... Control logic for the analog section of the ADC is clocked by CLK_ADCx, see also Figure 9. 6.15.5 Pulse Width Modulator (PWM) The MSCSS in the LPC2939 includes four PWM modules with the following features. LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Analog to digital converter pins ...

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... This makes the PWM function as a motor drive. LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 © NXP B.V. 2010. All rights reserved ...

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... Several PWMs can be synchronized using the trans_enable_in/trans_enable_out and sync_in/sync_out ports. See Figure 8 LPC2939. PWM 0 can be master over PWM 1; PWM 1 can be master over PWM 2, etc. LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB ...

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... A PWM module can use input signals trans_enable_in and sync_in to synchronize its internal PWM counter and the transfer of shadow registers (Slave mode). 6.15.5.4 Pin description Each of the four PWM modules in the MSCSS has the following pins. These are combined with other functions on the port pins of the LPC2939. pins. Table 24. Symbol ...

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... NXP Semiconductors 6.15.6.1 Pin description MSCSS timer 0 has no external pins. MSCSS timer 1 has a PAUSE pin available as external pin. The PAUSE pin is combined with other functions on the port pins of the LPC2939. external pin. Table 25. Symbol MSCSS PAUSE 6.15.6.2 Clock description The Timer modules in the MSCSS are clocked by CLK_MSCSS_MTMRx ( 1), see Section 6 ...

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... If the QEI is not used its CLK_MSCSS_QEI branch clock can be switched off. 6.16 Power, Clock and Reset control SubSystem (PCRSS) The Power, Clock and Reset Control Subsystem in the LPC2939 includes a Clock Generator Unit (CGU), a Reset Generator Unit (RGU), and a Power Management Unit (PMU). ...

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... FDIV[6:0] OUT7 OUT9 RGU RESET OUTPUT DELAY LOGIC INPUT DEGLITCH/ SYNC Section 6.7.2. CLK_SYS_PCRSS is derived from All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 PMU CGU1 OUT0 OUT1 OUT2 branch CLOCK clocks GATES AHB master disable: CLOCK ...

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... Maximum frequency that guarantees stable operation of the LPC2939. [2] Fixed to low-power oscillator. For generation of these base clocks, the CGU consists of primary and secondary clock generators and one output generator for each base clock. LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB ...

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... FDIV0 FDIV1 FDIV6 CLOCK DETECTION AHB TO DTL BRIDGE Table 27 for all base clocks) Figure 12. All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 OUT 0 BASE_SAFE_CLK BASE_SYS_CLK OUT 1 OUT 2 BASE_PCR_CLK OUT 3 BASE_IVNSS_CLK OUT 11 BASE_ICLK1_CLK 002aae147 © NXP B.V. 2010. All rights reserved. ...

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... For every output generator generating the base clocks a LP_OSC EXTERNAL OSCILLATOR PLL Every secondary clock generator or output generator is Clocks that are inactive are automatically regarded as invalid, All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 FDIV0:6 clkout clkout120 clkout240 OUTPUT CONTROL clock outputs 002aad834 © ...

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... Figure 14. The input clock is fed directly to the . These clocks are either divided by 2  the programmable post 2 All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Table 36, Dynamic characteristics. © NXP B.V. 2010. All rights reserved ...

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... Power-down mode the LOCK output is LOW, indicating that the PLL is not in lock. When Power-down mode is terminated by clearing the PD control-register bit the PLL resumes normal operation, and makes the LOCK signal HIGH once it has regained lock on the input clock. 6.16.2.3 Pin description The CGU0 module in the LPC2939 has the pins listed in Table 28. Symbol XOUT_OSC XIN_OSC ...

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... PLL clkout240 BASE_ICLK1_CLK Fig 15. Block diagram of the CGU1 6.16.3.1 Pin description The CGU1 module in the LPC2939 has the pins listed in Table 29. Symbol CLK_OUT 6.16.4 Reset Generation Unit (RGU) The RGU controls all internal resets. The key features of the Reset Generation Unit (RGU) are: • ...

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... MSCSS_TMR_RST I2C_RST QEI_RST DMA_RST USB_RST VIC_RST AHB_RST 6.16.4.2 Pin description The RGU module in the LPC2939 has the following pins. LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Reset output configuration Reset source power-on reset module POR_RST, RST pin RGU_RST, WATCHDOG PCR internal; source for COLD_RST ...

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... Using the base clocks from the CGU as input, the PMU generates branch clocks to the rest of the LPC2939. Output clocks branched from the same base clock are phase- and frequency-related. These branch clocks can be individually controlled by software programming ...

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... BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_PCR_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Implemented switch on/off mechanism WAKE-UP AUTO RUN ...

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... CLK_TMR2 CLK_TMR3 CLK_ADC0 CLK_ADC1 CLK_ADC2 CLK_USB_I2C CLK_USB 6.17 Vectored interrupt controller The LPC2939 contains a very flexible and powerful Vectored Interrupt Controller (VIC) to interrupt the ARM processor on request. The key features are: • Level-active interrupt request with programmable polarity • 56 interrupt-request inputs • ...

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... Software emulation of an interrupt-requesting device, including interrupts 6.17.2 Clock description The VIC is clocked by CLK_SYS_VIC, see LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Section All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 6.7.2. © NXP B.V. 2010. All rights reserved ...

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... I/O port 2 pins 12 and 13; I/O port 3 pins 0 and 1. average value per input pin drive HIGH, output shorted to V SS(IO) drive LOW, output shorted to VDD(IO) All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Min Max [1] - 1.5 0.5 +2.0 0.5 +2.0 0.5 +4.6 0.5 +6.0  ...

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... ARM9 microcontroller with CAN, LIN, and USB Conditions on all pins human body model charged device model on corner pins charged device model . I(ADC) . All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Min Max Unit 2000 [9] +2000 V 500 +500 V 750 ...

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... DD(IO) not applied 0.5 all other I/O pins, RST, TRST, TDI, JTAGSEL, TMS, TCK all port pins, RST, TRST, 2.0 TDI, JTAGSEL, TMS, TCK All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 = 3 5.5 V; DDA(ADC5V0) Typ Max Unit 1.80 1. A ...

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... V external pull-up  0 20.8 OH DD(IO) without 33  external series resistor  0 4.8 OH DD(IO) with 33 external series resistor All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 = 3 5.5 V; DDA(ADC5V0) Typ Max Unit - 0   A ...

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... DDA(ADC5V0) DDA(ADC3V3) . I(ADC) are the two external load capacitors. ext for 2 s before reset is de-asserted; V must be above V DD(CORE) trip(high) All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 = 3 5.5 V; DDA(ADC5V0) Min Typ Max 26.7 - 57.2 5 ...

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... T ADC and the ideal transfer curve. See [8] See Figure 16. ADC IN[y] Fig 16. Suggested ADC interface - LPC2939 ADC1/2 IN[y] pin LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB    +85 C unless otherwise specified ...

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... LSB (ideal) 1018 (LSB ) IA ideal All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 offset error E O (1) 1019 1020 1021 1022 1023 1024 002aae703 © NXP B.V. 2010. All rights reserved. gain error ...

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... MHz 0 1 C; active mode entered executing code from flash; all peripherals enabled amb at different core voltages V DD(CORE) All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 002aae241 90 130 core frequency (MHz) 002aae240 1.8 core voltage (V) (active mode) DD(CORE) © ...

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... MHz 0 −40 − different temperatures (active mode) DD(CORE) 85 °C 25 °C 0 °C −40 °C 0 1.0 2.0 3.0 = 3.3 V. DD(IO) All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 002aae239 temperature (°C) 002aae689 4.0 5.0 6.0 I (mA) OL © NXP B.V. 2010. All rights reserved ...

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... Fig 23. Typical pull-down input current versus temperature LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB 1.0 2.0 3.0 = 3.3 V. DD(IO) −40 − 3 All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 002aae690 85 °C 25 °C 0 °C −40 °C 4.0 5.0 6.0 I (mA) OH 002aae691 V = 3.6 V DD(IO) 3 ...

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... LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) −40 − All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 002aae692 = 2.7 V 3 temperature (°C) © NXP B.V. 2010. All rights reserved ...

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... CCO; direct mode 156 - - [3] on TXDCn pin - = 25 C (final testing). Both pre-testing and final testing use correlated amb All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Typ Max Unit - 13 13 MHz - 125 MHz ...

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... Fig 25. Low-power ring oscillator thermal characteristics LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB −40 −15 10 All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 002aae373 1.9 V 1 temperature (°C) © NXP B.V. 2010. All rights reserved. ...

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... Figure 26 see Figure must reject as EOP; see Figure 26 must accept as EOP; see Figure 26 crossover point extended SE0/EOP skew + t PERIOD FDEOP All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Min Typ Max 8.5 - 13.8 7 109 1.3 - 2.0 160 - 175  ...

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... SPI Master mode; see Figure C (final testing). Both pre-testing and final testing use correlated amb t su(SPI_MISO) All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 [2] Min Typ Max 20 + 0.1  C ambient amb = 3 5.5 V ...

Page 78

... DD(CORE) DD(OSC_PLL 3.6 V; all voltages are measured with respect to ground. Parameter Conditions clock frequency endurance retention time powered All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 ; 3.6 V; DD(IO) Min Typ Max [1] 10000 - - ...

Page 79

... Both pre-testing and final testing use correlated amb All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Typ Max Unit - 100 - 20 24.9 ns 2.5 - 2.5  WSTOEN  CLCL CLCL 0 + WSTOEN  T ...

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... ARM9 microcontroller with CAN, LIN, and USB t CSLAV t su(DQ OELAV BLSLAV OELOEH BLSLBLSH t CSLDV t BLSLBLSH t CSLBLSL t t CSLWEL WELWEH t WELDV t CSLDV All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 t CSHOEH t h(D) 002aae687 t CSHBLSH 002aae688 © NXP B.V. 2010. All rights reserved ...

Page 81

... Duty cycle clock should be as close as possible 10. Application information 10.1 Operating frequency selection The LPC2939 is specified to operate at a maximum frequency of 125 MHz, maximum temperature of 85 C, and maximum core voltage of 1.89 V. that the user can achieve higher operating frequencies for the LPC2939 by controlling the temperature and the core voltage accordingly ...

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... NXP Semiconductors 145 core frequency (MHz) 135 125 115 105 Fig 30. LPC2939 core operating frequency versus temperature for different core voltages 145 core frequency (MHz) 135 125 115 105 Fig 31. LPC2939 core operating frequency versus core voltage for different temperatures LPC2939_3 ...

Page 83

... NXP Semiconductors 10.2 Suggested USB interface solutions LPC29xx Fig 32. LPC2939 USB interface on a self-powered device LPC29xx Fig 33. LPC2939 USB interface on a bus-powered device LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) USB_UP_LED USB_CONNECT SoftConnect switch R1 1.5 kΩ USB_VBUS Ω ...

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... USB_INT1 USB_D+1 USB_D−1 USB_UP_LED1 LPC293X USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 34. LPC2939 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) RESET_N ADR/PSW OE_N/INT_N V DD(IO) ...

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... USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC293X USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 35. LPC2939 USB OTG port configuration: USB port 1 host, USB port 2 host LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) 33 Ω 33 Ω 15 kΩ 15 kΩ ...

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... USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC293X USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D−2 USB_VBUS2 Fig 36. LPC2939 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) 33 Ω 33 Ω 15 kΩ 15 kΩ ...

Page 87

... SDOn MSB OUT SDIn MSB IN DATA VALID SDOn MSB OUT DATA VALID All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 DATA VALID LSB OUT DATA VALID LSB IN LSB OUT LSB IN 002aae693 DATA VALID LSB IN DATA VALID ...

Page 88

... Product data sheet ARM9 microcontroller with CAN, LIN, and USB which attenuates the input voltage by a factor C g LPC29xx XIN_OSC C i 100 pF All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 / ( 002aae730 and C , and C ...

Page 89

... scale (1) ( 0.20 28.1 28.1 30.15 30.15 0.5 0.09 27.9 27.9 29.85 29.85 REFERENCES JEDEC JEITA MS-026 All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 detail 0.75 1.43 1.43 1 0.12 0.08 0.08 0.45 1.08 1.08 EUROPEAN ISSUE DATE PROJECTION ...

Page 90

... Solder bath specifications, including temperature and impurities LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 © NXP B.V. 2010. All rights reserved ...

Page 91

... Package reflow temperature (C) 3 Volume (mm ) < 350 260 260 250 Figure 41. All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Figure 41) than a SnPb process, thus  350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © ...

Page 92

... ARM9 microcontroller with CAN, LIN, and USB maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 peak temperature time 001aac844 © NXP B.V. 2010. All rights reserved ...

Page 93

... Power Control and Reset system PHYsical layer Phase-Locked Loop Power-On Reset Pulse-Width Modulator Quadrature Encoder Interface Queued-SPI Reduced Instruction Set Computer System Control Unit All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 © NXP B.V. 2010. All rights reserved ...

Page 94

... Serial Peripheral Interface Synchronous Serial Port Test Access Port Tightly-Coupled Memory Transistor-Transistor Logic Universal Asynchronous Receiver Transmitter Universal Serial Bus WatchDog Timer All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 © NXP B.V. 2010. All rights reserved ...

Page 95

... Pin description for pins 187 (GPIO 4, pin 15) and 188 (GPIO 5, pin 15) corrected. Product data sheet 3: Changed P1[31] to P1[30] for pin 29 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 Change notice Supersedes - LPC2939_2 - LPC2939_1 - - © NXP B.V. 2010. All rights reserved ...

Page 96

... It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 © NXP B.V. 2010. All rights reserved ...

Page 97

... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 © NXP B.V. 2010. All rights reserved ...

Page 98

... Clock description . . . . . . . . . . . . . . . . . . . . . . 51 6.16.2 Clock Generation Unit (CGU0 6.16.2.1 Functional description . . . . . . . . . . . . . . . . . . 52 6.16.2.2 PLL functional description . . . . . . . . . . . . . . . 55 6.16.2.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 56 6.16.3 Clock generation for USB (CGU1 6.16.3.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 57 All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 © NXP B.V. 2010. All rights reserved ...

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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC2939 All rights reserved. Date of release: 7 April 2010 Document identifier: LPC2939_3 ...