LPC2939 NXP Semiconductors, LPC2939 Datasheet - Page 40

• Manufacturer Part Number: LPC2939
• Description: The LPC2939 combine an ARM968E-S CPU core with two integrated TCM blocksoperating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2939_3
Product data sheet
6.14.3.1 Pin description
6.14.3 I
6.15 Modulation and Sampling Control SubSystem (MSCSS)
Table 21.
The LPC2939 each contain two I
The I
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or as a transmitter with
the capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
The main features if the I
Table 22.
[1]
The Modulation and Sampling Control Subsystem (MSCSS) in the LPC2939 includes four
Pulse-Width Modulators (PWMs), three 10-bit successive approximation Analog-to-Digital
Converters (ADCs) and two timers.
The key features of the MSCSS are:
Symbol
LIN0/1 TXD
LIN0/1 RXD
Symbol
I2C SCL0/1
I2C SDA0/1
2
•
•
•
•
•
•
•
•
•
•
C-bus serial I/O controllers
I
and do not support powering off of individual devices connected to the same bus lines
Easy to configure as master, slave, or master/slave
Programmable clocks allow versatile rate control
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
The I
All I
Note that the pins are not I
2
2
C0 and I
C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
2
C-bus controllers support multiple address recognition and a bus monitor mode
2
C-bus can be used for test and diagnostic purposes
LIN controller pins
I
2
C-bus pins
Pin name
TXDL0/1
RXDL0/1
Pin name
SCL0/1
SDA0/1
2
C1 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I
All information provided in this document is subject to legal disclaimers.
[1]
Rev. 03 — 7 April 2010
2
2
C-bus interfaces are:
C-bus compliant open-drain pins.
Direction
OUT
IN
Direction
I/O
I/O
2
C-bus controllers.
ARM9 microcontroller with CAN, LIN, and USB
Description
LIN channel 0/1 transmit data output
LIN channel 0/1 receive data input
Description
I
I
2
2
C clock input/output
C data input/output
2
C is a multi-master bus, and it can be
LPC2939
© NXP B.V. 2010. All rights reserved.
2
C-bus)
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