LPC2939 NXP Semiconductors, LPC2939 Datasheet - Page 36

• Manufacturer Part Number: LPC2939
• Description: The LPC2939 combine an ARM968E-S CPU core with two integrated TCM blocksoperating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2939_3
Product data sheet
6.13.4.2 Clock description
6.13.5.1 Functional description
6.13.5 Serial peripheral interface (SPI)
The UART modules are clocked by two different clocks; CLK_SYS_PESS and
CLK_UARTx (x = 0 to 1), see
CLK_UARTx branch clock for power management. The frequency of all CLK_UARTx
clocks is identical since they are derived from the same base clock BASE_CLK_UART.
The register interface towards the system bus is clocked by CLK_SYS_PESS. The baud
generator is clocked by the CLK_UARTx.
The LPC2939 contains three Serial Peripheral Interface modules (SPIs) to allow
synchronous serial communication with slave or master peripherals.
The key features are:
The SPI module can operate in:
The SPI module is a master or slave interface for synchronous serial communication with
peripheral devices that have either Motorola SPI or Texas Instruments Synchronous
Serial Interfaces.
The SPI module performs serial-to-parallel conversion on data received from a peripheral
device. The transmit and receive paths are buffered with FIFO memories (16 bits wide 
32 words deep). Serial data is transmitted on pins SDOx and received on pins SDIx.
The SPI module includes a programmable bit-rate clock divider and prescaler to generate
the SPI serial clock from the input clock CLK_SPIx.
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Master or slave operation
Each SPI supports up to four slaves in sequential multi-slave operation
Supports timer-triggered operation
Programmable clock bit rate and prescale based on SPI source clock
(BASE_SPI_CLK), independent of system clock
Separate transmit and receive FIFO memory buffers; 16 bits wide, 32 locations deep
Programmable choice of interface operation: Motorola SPI or Texas Instruments
Synchronous Serial Interfaces
Programmable data-frame size from 4 to 16 bits
Independent masking of transmit FIFO, receive FIFO and receive overrun interrupts
Serial clock-rate master mode: fserial_clk  f
Serial clock-rate slave mode: fserial_clk = f
Internal loopback test mode
Master mode:
– Normal transmission mode
– Sequential slave mode
Slave mode
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 7 April 2010
Section
6.7.2. Note that each UART has its own
ARM9 microcontroller with CAN, LIN, and USB
clk(SPI)
clk(SPI)
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LPC2939
© NXP B.V. 2010. All rights reserved.
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