STM32F103ZC STMicroelectronics, STM32F103ZC Datasheet - Page 18
Manufacturer Part Number
Mainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
Specifications of STM32F103ZC
ARM 32-bit Cortex™-M3 CPU
0 to 3.6 V
12-channel DMA controller
timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
a 24-bit downcounter
The STM32F103xC, STM32F103xD and STM32F103xE performance line supports three
low-power modes to achieve the best compromise between low power consumption, short
startup time and available wakeup sources:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for
DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to-
peripheral transfers. The two DMA controllers support circular buffer management,
removing the need for user code intervention when the controller reaches the end of the
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I
and advanced-control timers TIMx, DAC, I
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
registers used to store 84 bytes of user application data when V
They are not reset by a system or power reset, and they are not reset when the device
wakes up from the Standby mode.
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
supply when present or through the V
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Doc ID 14611 Rev 8
S, SDIO and ADC.
STM32F103xC, STM32F103xD, STM32F103xE
pin. The backup registers are forty-two 16-bit
C, USART, general-purpose, basic
power is not present.