STM32F103ZC STMicroelectronics, STM32F103ZC Datasheet - Page 80

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STM32F103ZC

Manufacturer Part Number
STM32F103ZC
Description
Mainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F103ZC

Core
ARM 32-bit Cortex™-M3 CPU
Conversion Range
0 to 3.6 V
Dma
12-channel DMA controller
Supported Peripherals
timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
Systick Timer
a 24-bit downcounter

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Electrical characteristics
Table 39.
1. C
2. Based on characterization, not tested in production.
80/130
t
t
t
t
t
t
t
t
t
t
t
t
t
w(NIOWR)
v(NIOWR-D)
h(NIOWR-D)
d(NCE4_1-NIOWR)
h(NCEx-NIOWR)
h(NCE4_1-NIOWR)
d(NIORD-NCEx)
d(NIORD-NCE4_1)
h(NCEx-NIORD)
h(NCE4_1-NIORD)
su(D-NIORD)
d(NIORD-D)
w(NIORD)
Symbol
L
= 15 pF.
Switching characteristics for PC Card/CF read and write cycles
NAND controller waveforms and timings
Figure 38
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
FSMC_NIOWR low width
FSMC_NIOWR low to FSMC_D[15:0] valid
FSMC_NIOWR high to FSMC_D[15:0] invalid
FSMC_NCE4_1 low to FSMC_NIOWR valid
FSMC_NCEx high to FSMC_NIOWR invalid
FSMC_NCE4_1 high to FSMC_NIOWR invalid
FSMC_NCEx low to FSMC_NIORD valid FSMC_NCE4_1
low to FSMC_NIORD valid
FSMC_NCEx high to FSMC_NIORD invalid
FSMC_NCE4_1 high to FSMC_NIORD invalid
FSMC_D[15:0] valid before FSMC_NIORD high
FSMC_D[15:0] valid after FSMC_NIORD high
FSMC_NIORD low width
COM.FSMC_SetupTime = 0x01;
COM.FSMC_WaitSetupTime = 0x03;
COM.FSMC_HoldSetupTime = 0x02;
COM.FSMC_HiZSetupTime = 0x01;
ATT.FSMC_SetupTime = 0x01;
ATT.FSMC_WaitSetupTime = 0x03;
ATT.FSMC_HoldSetupTime = 0x02;
ATT.FSMC_HiZSetupTime = 0x01;
Bank = FSMC_Bank_NAND;
MemoryDataWidth = FSMC_MemoryDataWidth_16b;
ECC = FSMC_ECC_Enable;
ECCPageSize = FSMC_ECCPageSize_512Bytes;
TCLRSetupTime = 0;
TARSetupTime = 0;
through
Figure 41
Parameter
represent synchronous waveforms and
Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE
8t
11t
5t
5t
4.5
9
8t
HCLK
HCLK
HCLK
HCLK
HCLK
Min
+ 3
– 5
– 5
+ 2
(1)(2)
Table 40
5t
5t
5t
(continued)
HCLK
HCLK
HCLK
Max
provides the
+3ns
+1
+ 2.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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