ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet

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... Instruction set – 8-bit data manipulation – 63 basic instructions with illegal opcode detection – 17 main addressing modes – unsigned multiply instructions ■ Development tools – Full HW/SW development package – DM (Debug module) Rev 4 ST7LITE49K2 LQFP32 PDIP32S www.st.com 1/245 1 ...

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... Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.1 5.3.2 5.4 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.4.1 5.4.2 5.4.3 5.5 Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.6 Data EEPROM read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.7 EEPROM control/status register (EECSR 2/245 In-circuit programming (ICP In-application programming (IAP Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Read operation (E2LAT= Write operation (E2LAT= Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ST7LITE49K2 ...

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... ST7LITE49K2 6 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 7 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.1 RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.1.1 7.1.2 7.2 Multi-oscillator (MO 7.2.1 7.2.2 7.2.3 7.3 Reset sequence manager (RSM 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 System integrity management (SI 7.4.1 7.4.2 7.4.3 7.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Accumulator ( Index registers (X and Program counter (PC Condition code register (CC) ...

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... Interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Interrupt software priority registers (ISPRx External interrupt control register (EICR Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 AWUFH control/status register (AWUCSR AWUFH prescaler register (AWUPR Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 ST7LITE49K2 ...

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... ST7LITE49K2 10.7.1 10.7.2 11 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11.1 Watchdog timer (WDG 11.1.1 11.1.2 11.1.3 11.1.4 11.1.5 11.1.6 11.2 Dual 12-bit autoreload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.3 Lite timer 2 (LT2 109 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.4 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.4.6 11.4.7 11.4 bus interface (I 11.5.1 11.5.2 Standard ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Other ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Interrupts ...

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... Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Immediate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Direct modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Indexed modes (no offset, short, long 185 Indirect modes (short, long 186 ST7LITE49K2 ...

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... ST7LITE49K2 12.1.6 12.1.7 12.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 12.2.1 13 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.1.1 13.1.2 13.1.3 13.1.4 13.1.5 13.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 13.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 13.4.1 13.4.2 13.5 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 203 13.5.1 13.5.2 13.6 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 13.6.1 13.6.2 13.6.3 13.7 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 13.8 EMC (electromagnetic compatibility) characteristics . . . . . . . . . . . . . . . 212 13.8.1 13.8.2 13.8.3 13.9 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 13 ...

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... Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 15.1 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 8/245 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Option byte 230 Option byte 231 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Order codes for development and programming tools . . . . . . . . . . . . . 236 ST7LITE49K2 ...

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... ST7LITE49K2 List of tables Table 1. ST7LITE49K2 device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 2. ST7LITE49K2 device pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 3. Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 4. Interrupt software priority truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 5. Predefined RC oscillator calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 6. ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 7. CPU clock delay during Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 8. Low power modes Table 9 ...

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... ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Table 95. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Table 96. General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Table 97. Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Table 98. Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Table 99. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Table 100. ADC accuracy with VDD = 3 227 10/245 2 C interface 204 ST7LITE49K2 ...

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... Table 108. Selection of the resonator oscillator range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Table 109. Configuration of sector size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Table 110. Development tool order codes for the ST7LITE49K2 family 237 Table 111. ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Table 112. 32-pin plastic dual in-line package, shrink 400-mil width, mechanical data . . . . . . . . . . . 241 Table 113 ...

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... Figure 40. PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 41. PWM signal from 0% to 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 42. Dead time generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 43. ST7LITE49K2 block diagram of break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 44. Block diagram of output compare mode (single timer Figure 45. Block diagram of input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 46. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 47. ...

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... Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Figure 78. Clearing the WCOL bit (write collision flag) software sequence . . . . . . . . . . . . . . . . . . . . 164 Figure 79. Single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Figure 80. ST7LITE49K2 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Figure 81. Analog comparator and internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Figure 82. Analog comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Figure 83. ...

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... Figure 124. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Figure 125. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Figure 126. ST7LITE49K2 ordering information scheme 233 Figure 127. 32-pin plastic dual in-line package, shrink 400-mil width, package outline 241 Figure 128. 32-pin low profile quad flat package (7x7), package outline . . . . . . . . . . . . . . . . . . . . . . . 242 14/245 = 2 mA (standard) ...

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... ST7LITE49K2 1 Description The ST7LITE49K2 is a member of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. The ST7LITE49K2 features Flash memory with byte-by-byte In-Circuit Programming (ICP) and In-Application Programming (IAP) capability. Under software control, the ST7LITE49K2 device can be placed in Wait, Slow, or Halt mode, reducing power consumption when the application is in idle or standby state ...

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... Description Figure 1. ST7LITE49K2 general block diagram CLKIN OSC_IN OSC_OUT RESET 16/245 PLL 8 MHz -> 32 MHz / 2 Ext. OSC / 2 1 MHz to Internal 16 MHz clock Int. 8 MHz RC OSC Int. 32 kHz RC OSC LVD, AVD Power supply Control 8-bit core ALU Flash program memory ...

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... ST7LITE49K2 2 Pin description Figure 2. 32-pin SDIP package pinout COMPOUTA/BREAK1/PC7 ATPWM2/MCO/PA4(HS) Note 1: Available on 8K version only Figure 3. 32-pin LQFP 7x7 package pinout ATPWM1/PA3(HS) ATPWM2/MCO/PA4(HS) ATPWM3/PA5(HS) I2CDATA/PA6(HS) I2CCLK/PA7(HS) 1 ei2 PA0(HS)/COMPINA- 2 ei2 ATIC/PA1(HS) 3 ATPWM0/PA2(HS) 4 ATPWM1/PA3(HS) 5 ei0 6 ei2 ATPWM3/PA5(HS) 7 I2CDATA/PA6(HS) 8 I2CCLK/PA7(HS) 9 RESET ei1 ...

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... Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog ● Output open drain push-pull The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state. Table 2. ST7LITE49K2 device pin description Pin number Pin name 1 5 PA3(HS)/ATPWM1 I/O ...

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... ST7LITE49K2 Table 2. ST7LITE49K2 device pin description Pin number Pin name 14 18 PB0/AIN0 15 19 PB1/AIN1/CLKIN 16 20 PB2/AIN2 17 21 PB3/AIN3/MOSI 18 22 PB4/AIN4/MISO PB5/AIN5 EXTCLK_A/ COMPOUTB 20 24 PB6/AIN6/SCK PB7/AIN7/SS OCMP2_A PC0/AIN8 ICAP1_A PC1/AIN9 ICAP2_A 24 28 PC2/ICCDATA 25 29 PC3/ICCCLK Level Port/control ...

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... Pin description Table 2. ST7LITE49K2 device pin description Pin number Pin name PC4/LTIC COMPINB- PC5/COMPINB BREAK2 28 32 PC6/COMPINA+ PC7/BREAK1 COMPOUTA PA0 /COMPINA /OCMP1_A 31 3 PA1(HS)/ATIC 32 4 PA2(HS)/ATPWM0 I the open-drain output column, T defines a true open-drain I/O (P-Buffer and protection diode to V implemented) ...

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... ST7LITE49K2 3 Register and memory mapping As shown in Figure registers. The available memory locations consist of 128 bytes of register locations, 384 bytes of RAM, 256 bytes of data EEPROM and 8 Kbytes of Flash program memory. The RAM space includes up to 128 bytes for the stack from 180h to 1FFh. ...

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... Reserved area (1 byte) Watchdog Control register Flash Control/Status register Data EEPROM Control/Status register A/D Control Status register A/D Data register High A/D Amplifier Control/Data Low Register Reserved area (1 byte) Main Clock Control/Status register ST7LITE49K2 Reset status Remarks 0x00 0000b R/W 00h Read Only 00h Read Only ...

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... ST7LITE49K2 Table 3. Hardware register map Address Block Register label RCCR 003Bh SICSR 003Ch Clock and Reset 003Dh AVDTHCR 003Eh to 0047h 0048h AWUCSR AWU 0049h AWUPR 004Ah DMCR 004Bh DMSR 004Ch DMBK1H (2) 004Dh DM DMBK1L 004Eh DMBK2H 004Fh DMBK2L 0050h DMCR2 Clock 0051h ...

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... Register and memory mapping 1. Legend: x=undefined, R/W=read/write. 2. For a description of the Debug Module registers, see ICC protocol reference manual. Figure 4. ST7LITE49K2 memory map 0000h HW registers 007Fh 0080h RAM (384 bytes) 01FFh 0200h Reserved 0FFFh 1000h Data EEPROM (256 bytes) 10FFh 1100h Reserved ...

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... ST7LITE49K2 4 Flash programmable memory 4.1 Introduction The ST7 single voltage extended Flash (XFlash non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or on- board using In-Circuit Programming or In-Application Programming ...

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... Caution: During normal operation the ICCCLK pin must be internally or externally pulled- up (external pull- kΩ mandatory in noisy environment) to avoid entering ICC mode unexpectedly 26/245 ST7LITE49K2 Ω schottky diode can be used Ω ...

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... ST7LITE49K2 during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up. Figure 5. Typical ICC Interface (See Note 3) APPLICATION POWER SUPPLY PROGRAMMING TOOL ICC CONNECTOR ICC Cable ICC CONNECTOR HE10 CONNECTOR TYPE OPTIONAL (See Note ...

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... RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh) When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically. Reset value: 000 0000 (00h 28/245 Read/write ST7LITE49K2 . 0 OPT LAT PGM ...

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... ST7LITE49K2 5 Data EEPROM 5.1 Introduction The electrically erasable programmable read only memory can be used as a non volatile back-up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. 5.2 Main features ● bytes programmed in the same cycle ● EEPROM mono-voltage (charge pump) ● ...

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... Data EEPROM programming flowchart 30/245 READ MODE E2LAT=0 E2PGM=0 WRITE BYTES READ BYTES IN EEPROM AREA (with the same 11 MSB of the address) START PROGRAMMING CYCLE E2PGM=1 (set by software) CLEARED BY HARDWARE ST7LITE49K2 Figure 7 describes these Figure WRITE MODE E2LAT=1 E2PGM=0 IN EEPROM AREA E2LAT E2LAT ...

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... ST7LITE49K2 Figure 8. Data EEPROM write operation ROW DEFINITION Byte 1 E2LAT bit Set by USER application E2PGM bit programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed. 5.4 Power saving modes 5.4.1 Wait mode The DATA EEPROM can enter Wait mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active-Halt mode ...

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... Programming cycle is in progress Note: If the E2PGM bit is cleared during the programming cycle, the memory data is not guaranteed. 32/245 READ OPERATION NOT POSSIBLE WRITE CYCLE ERASE CYCLE t PROG Read/write ST7LITE49K2 Section 14.1: Option bytes). READ OPERATION POSSIBLE LAT PGM 0 0 E2LAT E2PGM ...

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... ST7LITE49K2 6 Central processing unit 6.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 6.2 Main features ● 63 basic instructions ● Fast 8-bit by 8-bit multiply ● 17 main addressing modes ● Two 8-bit index registers ● ...

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... This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction reset by hardware during the same instructions half carry has occurred half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. 34/245 Read/write ST7LITE49K2 ...

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... ST7LITE49K2 Bit Interrupt mask bit This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions ...

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... A subroutine call occupies two locations and an interrupt five locations in the stack area. 36/245 Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable Read/write Figure ST7LITE49K2 SP6 SP5 SP4 SP3 SP2 SP1 SP0 11 ...

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... ST7LITE49K2 Figure 11. Stack manipulation example CALL Subroutine @ 0180h SP SP PCH @ 01FFh PCL Stack Higher Address = 01FFh Stack Lower Address = 0180h PUSH Y POP Y Interrupt Event PCH PCH PCH PCL PCL PCL PCH PCH PCH PCL PCL PCL ...

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... EEPROM for 3 and Table 5). Table 5. Predefined RC oscillator calibration values RCCR RCCRH0 RCCRL0 RCCRH1 RCCRL1 38/245 Conditions 25° MHz 3 25° MHz RC ST7LITE49K2 supply voltages at 25 °C (see DD ST7LITE49K2 Address (1) DEE0h (CR[9:2]) (1) DEE1h (CR[1:0]) (1) DEE2h (CR[9:2]) (1) DEE3h (CR[1:0]) ...

Page 39

... Refer to application note AN1324 for information on how to calibrate the RC frequency using an external reference signal. 7.1.2 Auto-wakeup RC oscillator The ST7LITE49K2 also contains an Auto-wakeup RC oscillator. This RC oscillator should be enabled to enter Auto-wakeup from halt mode. The Auto-wakeup (AWU) RC oscillator can also be configured as the startup clock through the CKSEL[1:0] option bits (see This is recommended for applications where very low power consumption is required ...

Page 40

... When the internal RC is selected, the AWU RC is turned on by hardware when entering Auto-wakeup from Halt mode. 3 When the external clock is selected, the AWU RC oscillator is always on. Figure 12. Clock switching 40/245 Set RC/AWU Internal RC Poll AWU_FLAG until set Reset RC/AWU AWU RC Internal RC Poll RC_FLAG until set ST7LITE49K2 AWU RC ...

Page 41

... ST7LITE49K2 Figure 13. Clock management block diagram CK2 CK1 CR9 CR8 Prescaler CLKSEL[1:0] Option bits CLKIN CLKIN CLKIN CLKIN OSC /OSC1 1-16 MHz or 32 kHz OSC2 f OSC /32 DIVIDER AVDTHCR CK0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 Tunable RC Oscillator 8 MHz ( AWU RC OSC ...

Page 42

... These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. 7.2.3 Internal RC oscillator In this mode, the tunable 1% RC oscillator is used as main clock source. The two oscillator pins have to be tied to ground. The calibration is done through the RCCR[7:0] and SICSR[6:5] registers. 42/245 ST7LITE49K2 ...

Page 43

... ST7LITE49K2 Table 6. ST7 clock sources 7.3 Reset sequence manager (RSM) 7.3.1 Introduction The reset sequence manager includes three RESET sources as shown in ● External RESET source pulse ● Internal LVD RESET (Low Voltage Detection) ● Internal WATCHDOG RESET Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. ...

Page 44

... External Crystal/Ceramic 32 kHz Oscillator Figure 14. Reset sequence phases 44/245 Clock source Internal RC 8 MHz Oscillator Internal RC 32 kHz Oscillator RESET Internal reset active phase 256 or 4096 clock cycles ST7LITE49K2 CPU clock cycle delay 4096 256 4096 4096 4096 256 Fetch vector ...

Page 45

... ST7LITE49K2 7.3.2 Asynchronous external RESET pin The RESET pin is both an input and an open-drain output with integrated R resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details. ...

Page 46

... V IT+(LVD) V IT-(LVD) EXTERNAL RESET SOURCE RESET PIN WATCHDOG RESET 46/245 . w(RSTL)out LVD RESET RUN RUN ACTIVE PHASE t h(RSTL)in WATCHDOG UNDERFLOW ST7LITE49K2 EXTERNAL WATCHDOG RESET RESET RUN RUN ACTIVE ACTIVE PHASE PHASE t w(RSTL)out INTERNAL RESET (256 or 4096 T VECTOR FETCH ) CPU ...

Page 47

... ST7LITE49K2 7.4 System integrity management (SI) The System Integrity Management block contains the Low voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions managed by the SICSR register. Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to Section 12.2.1 on page 189 7 ...

Page 48

... WATCHDOG TIMER (WDG) SYSTEM INTEGRITY MANAGEMENT MANAGER SICSR (RSM) 0 CR1 CR0 main supply voltage (V DD main supply DD threshold (AVDF bit is set). ST7LITE49K2 STATUS FLAG AVD Interrupt Request WDGF 0 LVDRF AVDF AVDIE LOW VOLTAGE DETECTOR (LVD) AUXILIARY VOLTAGE DETECTOR (AVD) ). The V ...

Page 49

... ST7LITE49K2 Note: Make sure that the right combination of LVD and AVD thresholds is used as LVD and AVD levels are not correlated. Refer to 196 for more details. Figure 19. Using the AVD to monitor IT+(AVD) V IT-(AVD) V IT+(LVD) V IT-(LVD) AVDF bit ...

Page 50

... To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h. 50/245 0 0 Read/write or f /32. OSC OSC f CPU = OSC f /32) CPU = OSC CR7 CR6 CR5 Read/write ST7LITE49K2 0 0 MCO CR4 CR3 Chapter 0 SMS 0 CR2 7.5.3. ...

Page 51

... ST7LITE49K2 7.5.3 System integrity (SI) control/status register (SICSR) Reset value: 011x 0x00 (xxh CR1 Bit 7 = Reserved, must be kept cleared Bits 6:5 = CR[1:0] RC oscillator frequency adjustment bits These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. Refer to Section 7 ...

Page 52

... They are set and cleared by software. They are set by hardware after a reset. Table 12. AVD threshold selection bits AVD1 AVD0 52/245 CK0 0 0 Read/write and Table 11. CK0 ST7LITE49K2 0 AVD1 Figure 13: Clock management block f OSC f RC/2 f RC/4 f RC/8 f RC/ Functionality Low Medium High AVD off 0 AVD0 ...

Page 53

... ST7LITE49K2 7.5.5 Clock controller control/status register (CKCNTCSR) Reset value: 0000 1001 (09h Bits 7:4 = Reserved, must be kept cleared. Bit 3 = AWU_FLAG AWU selection bit This bit is set and cleared by hardware switch from AWU to RC requested 1: AWU clock activated and temporization completed Bit 2 = RC_FLAG RC selection bit This bit is set and cleared by hardware ...

Page 54

... The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume. 54/245 Figure 20. ST7LITE49K2 ...

Page 55

... ST7LITE49K2 Table 14. Interrupt software priority levels Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Figure 20. Interrupt processing flowchart RESET RESTORE PC FROM STACK Level Low High PENDING Y INTERRUPT Interrupt has the same lower software priority than current one ...

Page 56

... The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details. 56/245 PENDING INTERRUPTS Different Same SOFTWARE PRIORITY HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED Figure 20. ST7LITE49K2 ...

Page 57

... Note interrupt, that is not able to Exit from Halt mode, is pending with the highest priority when exiting Halt mode, this interrupt is serviced after the first one serviced. Table 18: ST7LITE49K2 interrupt Table 18: ST7LITE49K2 interrupt Figure 21. Interrupts mapping. mapping). When several ...

Page 58

... Figure 23 show two different interrupt management modes. The 23. The interrupt hardware priority is given in this order from the IT0 IT1 IT2 IT2 IT3 IT4 TLI IT0 IT1 IT2 IT3 IT4 IT4 ST7LITE49K2 SOFTWARE I1 PRIORITY LEVEL ...

Page 59

... ST7LITE49K2 8.5 Description of interrupt registers 8.5.1 CPU CC register interrupt bits Reset value: 111x 1010(xAh Bits I1, I0 Software interrupt priority bits These two bits indicate the current interrupt software priority (see These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx) ...

Page 60

... Function/Example Entering Halt mode Pop CC I1 Jump if I1:0 <> 11 I1:0 <> 11 Mem => CC Load Load Software trap Software NMI Wait for interrupt ST7LITE49K2 ISPRx bits (1) I1_0 and I0_0 bits I1_1 and I0_1 bits ... I1_13 and I0_13 bits ( ...

Page 61

... ST7LITE49K2 Table 18. ST7LITE49K2 interrupt mapping Source Number block RESET TRAP 0 AWU 1 AVD Auxiliary Voltage Detector interrupt 2 COMPA 3 COMPB 4 ei0 External interrupt 0 (Port A) 5 ei1 External interrupt 1 (Port B) 6 ei2 External interrupt 2 (Port C) AT timer input Capture/Output 7 AT TIMER ( timer overflow 1 interrupt ...

Page 62

... Interrupt sensitivity bits ISx1 ISx0 62/245 IS21 IS20 IS11 Read/write External interrupt sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge ST7LITE49K2 0 IS10 IS01 IS00 Table 19. Table 19. Table 19. Section : External interrupt ...

Page 63

... ST7LITE49K2 9 Power saving modes 9.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see ● Slow ● Wait (and Slow-Wait) ● Active-halt ● Auto-wakeup from Halt (AWUFH) ● Halt After a reset the normal operating mode is selected by default (Run mode). This mode ...

Page 64

... Reset service routine. The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 26 64/245 ) to the available supply voltage. CPU f OSC f CPU f OSC SMS for a description of the Wait mode flowchart. ST7LITE49K2 /32 f OSC NORMAL RUN MODE REQUEST ...

Page 65

... ST7LITE49K2 Figure 26. Wait mode flowchart 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 9.4 Active-halt and Halt modes Active-Halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘ ...

Page 66

... This means that the device cannot spend more than a defined delay in this power saving mode. Figure 27. Active-halt timing overview [Active-halt Enabled] 1. This delay occurs only if the MCU exits Active-Halt mode by means of a RESET. 66/245 Figure 28). ACTIVE RUN HALT CYCLE DELAY HALT INTERRUPT INSTRUCTION ST7LITE49K2 Figure 256 CPU RUN 1) RESET OR FETCH VECTOR 28). ...

Page 67

... HALT instruction when Active-halt mode is disabled. The MCU can exit Halt mode on reception of either a specific interrupt (see ST7LITE49K2 interrupt or an interrupt, the main oscillator is immediately turned on and the 256 CPU cycle delay is used to stabilize it. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the Reset vector which woke it up (see When entering Halt mode, the I bit in the CC register is forced enable interrupts ...

Page 68

... Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to Table 18: ST7LITE49K2 interrupt 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. ...

Page 69

... ST7LITE49K2 Halt mode recommendations ● Make sure that an external event is available to wake up the microcontroller from Halt mode. ● When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference unforeseen logical condition. ● ...

Page 70

... AWU_RC AWUFH interrupt 70/245 and then calculating the right prescaler value. AWU_RC to the Input Capture of the 8-bit Lite timer, allowing the AWU_RC Section 9.4: Active-halt and Halt t AWU HALT MODE ST7LITE49K2 ). Its frequency is divided by AWU_RC modes). 256 t RUN MODE CPU Clear by software ...

Page 71

... N 3) INTERRUPT AWU RC OSC Y MAIN OSC PERIPHERALS CPU I[1:0] BITS 256 CPU CLOCK CYCLE AWU RC OSC MAIN OSC PERIPHERALS CPU I[1:0] BITS FETCH RESET VECTOR OR SERVICE INTERRUPT Table 18: ST7LITE49K2 interrupt mapping Power saving modes WATCHDOG DISABLE ON OFF 2) OFF OFF 10 RESET Y OFF ON OFF ...

Page 72

... It is set and cleared by software. 0: AWUFH (Auto-wakeup from Halt) mode disabled 1: AWUFH (Auto-wakeup from Halt) mode enabled Note: Whatever the clock source, this bit should be set to enable the AWUFH mode once the HALT instruction has been executed. 72/245 Read/Write ST7LITE49K2 0 AWU AWUM AWUEN F ...

Page 73

... ST7LITE49K2 9.5.3 AWUFH prescaler register (AWUPR) Reset value: 1111 1111 (FFh) 7 AWUPR7 AWUPR6 Bits 7:0= AWUPR[7:0] Auto-wakeup prescaler These 8 bits define the AWUPR Dividing factor (see Table 21. Configuring the dividing factor AWUPR[7:0 00h 01h ... FEh FFh In AWU mode, the time during which the MCU stays in Halt mode, t equation below ...

Page 74

... External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. 74/245 ST7LITE49K2 ...

Page 75

... ST7LITE49K2 Spurious interrupts When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge detector input which is switched to '1' when the external interrupt is disabled by the OR register. ...

Page 76

... ALTERNATE ENABLE BIT If implemented 1 0 Combinational Logic FROM OTHER BITS Note: Refer to the Port Configuration table for device specific information. ST7LITE49K2 describes which peripheral signals can P-BUFFER V DD (see table below) PULL-UP (see table below PULL-UP PAD CONDITION N-BUFFER DIODES ...

Page 77

... ST7LITE49K2 Table 24. I/O port mode options Configuration mode Floating with/without Interrupt Input Pull-up with Interrupt Output Open Drain (logic level) 1. Off means implemented not activated, On means implemented and activated. Table 25. I/O port configuration PAD PAD PAD 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status ...

Page 78

... INPUT INPUT OUTPUT floating/pull-up floating open-drain interrupt (reset state) XX Description No effect on I/O ports. External interrupts cause the device to exit from Wait No effect on I/O ports. External interrupts cause the device to exit from Halt ST7LITE49K2 Figure 11 OUTPUT push-pull = DDR, OR Section 13.9: I/O port mode. mode. 35. ...

Page 79

... ST7LITE49K2 10.6 Interrupts The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM instruction). Table 27. Description of interrupt events Interrupt event External interrupt on selected external event See application notes AN1045 software implementation of software LCD driver 10 ...

Page 80

... ST7LITE49K2 DDR 1 1 Output open drain true open drain open drain open drain pull-up open drain ...

Page 81

... ST7LITE49K2 11 On-chip peripherals 11.1 Watchdog timer (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared ...

Page 82

... WDG reset immediately after waking up the microcontroller. Same behavior in active-halt mode. 11.1.5 Interrupts None. 82/245 timing): (1)( MHz CPU min [ms] 1 127 Table 33 is due to the unknown status of the prescaler when writing to the Section 14 on page ST7LITE49K2 max [ms] 2 128 230. ...

Page 83

... ST7LITE49K2 11.1.6 Register description Control register (WDGCR) Reset value: 0111 1111 (7Fh) 7 WDGA Bit 7 = WDGA Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. ...

Page 84

... Input Capture mode – 12-bit Input Capture register (ATICR) – Triggered by rising and falling edges – Maskable IC interrupt – Long range input capture ● Internal/external break control ● Flexible clock control ● One Pulse mode on PWM2/3 ● Force update 84/245 ) CPU ST7LITE49K2 ...

Page 85

... ST7LITE49K2 Figure 37. Single timer mode (ENCNTR2=0) ATIC Edge Detection Circuit 12-Bit Autoreload register 1 Clock Control Figure 38. Dual timer mode (ENCNTR2=1) Edge Detection Circuit ATIC 12-Bit Autoreload register 1 12-Bit Autoreload register 2 Control LTIC 12-bit Input Capture PWM0 Duty Cycle Generator PWM1 Duty Cycle Generator ...

Page 86

... DCRx register must be greater than the contents of the ATR register. 86/245 Figure 37 and Figure 38). The frequency is controlled by the counter ⁄ 4096 ATR = PWM COUNTER equals 4 MHz COUNTER ⁄ ( Resolution = 1 4096 ATR ST7LITE49K2 ) or can have two different PWM ) – the maximum value – is PWM ...

Page 87

... ST7LITE49K2 The maximum value of ATR is 4094 because it must be lower than the DCR value which must be 4095 in this case. ● Polarity inversion The polarity bits can be used to invert any of the four output signals. The inversion is synchronized with the counter overflow if the corresponding transfer bit in the ATCSR2 register is set (reset value) ...

Page 88

... OP0 and OP1 are not set. If polarity is inverted, overlapping PWM0/PWM1 signals will be generated. 3 Dead Time generation does not work at 1msec timebase. 88/245 ATR= FFDh FFDh FFEh FFFh FFDh [ ] × Dead time = DT 6:0 ST7LITE49K2 FFEh FFFh FFDh Tcounter1 ≠ DTE is set and DT[6:0]=0, FFEh t ...

Page 89

... ST7LITE49K2 Figure 42. Dead time generation CK_CNTR1 CNTR1 PWM 0 PWM 1 PWM 0 PWM 1 In the above example, when the DTE bit is set: ● PWM goes low at DCR0 match and goes high at ATR1+Tdt ● PWM1 goes high at DCR0+Tdt and goes low at ATR match. With this programmable delay (Tdt), the PWM0 and PWM1 signals which are generated are not overlapped ...

Page 90

... ATR1, ATR2, Preload and Active DCRx are put to their reset values. ● Counters stop counting. When the break function is deactivated after applying the break (BAx bit go from software), Timer takes the control of PWM ports. Figure 43. ST7LITE49K2 block diagram of break function BREAK1 pin Comparator1 BREAKCR2 register BR2SEL BR2EDGE ...

Page 91

... ST7LITE49K2 When the 12-bit upcounter CNTR1 reaches the value stored in the Active DCRxH and DCRxL registers, the CMPFx bit in the PWMxCSR register is set and an interrupt request is generated if the CMPIE bit is set. In Single Timer mode the output compare function is performed only on CNTR1. The ...

Page 92

... Refer to 92/245 12-BIT INPUT CAPTURE REGISTER ATICR IC INTERRUPT REQUEST ICF ICIE CK1 CK0 12-BIT UPCOUNTER1 CNTR1 12-BIT AUTORELOAD REGISTER ATR1 02h 03h 04h 05h 06h INTERRUPT xxh Figure 47. ST7LITE49K2 07h 08h 09h 0Ah INTERRUPT ATICR READ 09h 04h equals 8 OSC t ...

Page 93

... ST7LITE49K2 Figure 47. Long range input capture block diagram ICS LTIC 1 ATIC 0 Since the Input Capture flags (ICF) for both timers (AT4 timer and LT timer) are set when signal transition occurs, software must mask one interrupt by clearing the corresponding ICIE bit before setting the ICS bit. ...

Page 94

... F9 LT1 LT2 = – × ATICR2 ATICR1 + + 00h LT1 F9h 00h ATH1 & ATL1 00h 0h 00h ST7LITE49K2 ) × 1 0.004ms + ) × 1 1ms – – LT2 LT1 ATH1 ATL1 ATICR = ATICRH[3:0] & ATICRL[7: ATH2 & ATL2 ...

Page 95

... ST7LITE49K2 One pulse mode One pulse mode can be used to control PWM2/3 signal with an external LTIC pin. This mode is available only in Dual Timer mode i.e. only for CNTR2, when the OP_EN bit in PWM3CSR register is set. One Pulse mode is activated by the external LTIC input. The active edge of the LTIC pin is selected by the OPEDGE bit in the PWM3CSR register ...

Page 96

... Note 1: When OP_EN=0, LTIC edges are not taken into account as the timer runs in PWM mode. 96/245 OP_EN 12-bit AutoReload register 2 12-bit Active DCR2/3 000 DCR2/3 OVF ATR2 DCR2/3 OVF ST7LITE49K2 12-bit Upcounter 2 PWM Generation OP2/3 000 DCR2/3 ATR2 ATR2 DCR2/3 ATR2 ...

Page 97

... ST7LITE49K2 Figure 51. Dynamic DCR2/3 update in one pulse mode f counter2 CNTR2 LTIC FORCE2 TRAN2 DCR2/3 PWM2/3 Force update In order not to wait for the counter programmable counter which when set, make the counters start with the overflow value, i.e. FFFh. After overflow, the counters start counting from their respective auto reload register values. ...

Page 98

... Description No effect on AT timer AT timer halted. Event Enable Exit from flag control bit Wait OVF1 OVIE1 Yes ICF ICIE Yes OVF2 OVIE2 Yes ICIE CK1 CK0 Read / Write ST7LITE49K2 Exit from Exit from Halt Active-halt No Yes OVF1 OVFIE1 CMPIE ...

Page 99

... ST7LITE49K2 Bits 4:3 = CK[1:0] Counter clock selection bits These bits are set and cleared by software and cleared by hardware after a reset. they select the clock frequency of the counter. Table 37. Counter clock selection Bit 2 = OVF1 Overflow flag This bit is set by hardware and cleared by software by reading the ATCSR register. It indicates the transition of the Counter1 CNTR1 from FFFh to ATR1 value ...

Page 100

... PWM mode disabled. PWMx Output Alternate function disabled (I/O pin free for general purpose I/O) 1: PWM mode enabled 100/245 =f , special care must be taken when CNTR1L values timer CPU 0 0 ATR11 Read/write ATR5 ATR4 ATR3 Read/write 0 OE2 0 Read/write ST7LITE49K2 8 ATR10 ATR9 ATR8 0 ATR2 ATR1 ATR0 0 OE1 0 OE0 ...

Page 101

... ST7LITE49K2 PWMX control status register (PWMxCSR) Reset value: 0000 0000 (00h Bits 7:4= Reserved, must be kept cleared. Bit 3 = OP_EN One Pulse Mode Enable bit This bit is read/write by software and cleared by hardware after a reset. This bit enables the One Pulse feature for PWM2 and PWM3 (only available for PWM3CSR) 0: One Pulse mode disable for PWM2/3 ...

Page 102

... Bit 5 = BA2 Break 2 Active bit This bit is read/write by software, cleared by hardware after reset and set by hardware when the active level defined by the BR2EDGE bit is applied on the BREAK2 pin. It activates/deactivates the Break 2 function. 0: Break 2 not active 1: Break 2 active 102/245 BA2 BP2EN - Read/write ST7LITE49K2 0 - SWBR2 SWBR1 ...

Page 103

... ST7LITE49K2 Bit 4 = BP2EN Break 2 pin enable bit This bit is read/write by software and cleared by hardware after Reset. 0: BREAK2 pin disabled 1: BREAK2 pin enabled Bits 3:2 = Reserved, must be kept cleared Bit 1 = SWBR2 Switch Break for counter 2 bit This bit is read/write by software. While BREN2 is set, it selects BA1 or BA2 to control PWM2/3 if ENCNTR2 bit is set ...

Page 104

... PWM0/1 by default, and controls PWM2/3 also if ENCNTR2 bit is reset Break applied for CNTR1 1: Break applied for CNTR1 104/245 Read only ICR5 ICR4 Read only 0 0 Read/write ST7LITE49K2 ICR11 ICR10 ICR9 ICR3 ICR2 ICR1 0 0 BREN2 8 ICR8 0 ICR0 0 ...

Page 105

... ST7LITE49K2 Timer control register 2 (ATCSR2) Reset value: 0000 0011 (03h) 7 FORCE2 FORCE1 Bit 7 = FORCE2 Force counter 2 overflow bit This bit is read/set by software. When set, it loads FFFh in the CNTR2 register reset by hardware one CPU clock cycle after counter 2 overflow has occurred. ...

Page 106

... This is a 12-bit register which is written by software. The ATR2 register value is automatically loaded into the upcounter CNTR2 when an overflow of CNTR2 occurs. The register value is used to set the PWM2/PWM3 frequency when ENCNTR2 is set. 106/245 Read/write ATR5 ATR4 Read/write ST7LITE49K2 ATR11 ATR10 ATR9 ATR3 ATR2 ATR1 8 ATR8 0 ATR0 ...

Page 107

... ST7LITE49K2 Dead time generator register (DTGR) Reset value: 0000 0000 (00h) 7 DTE DT6 Bit 7 = DTE Dead time enable bit This bit is read/write by software. It enables a dead time generation on PWM0/PWM1 Dead time insertion. 1: Dead time insertion enabled. Bits 6:0 = DT[6:0] Dead time value These bits are read/write by software. They define the dead time inserted between PWM0/PWM1 ...

Page 108

... BA BPEN ATR6 ATR5 ATR4 DT6 DT5 DT4 Reserved area BR2EDGE BA2 BP2EN ST7LITE49K2 DCR3 DCR2 DCR1 DCR11 DCR10 DCR9 DCR3 DCR2 DCR1 DCR11 DCR10 DCR9 DCR3 DCR2 DCR1 ...

Page 109

... ST7LITE49K2 11.3 Lite timer 2 (LT2) 11.3.1 Introduction The Lite timer can be used for general-purpose timing functions based on two free- running 8-bit upcounters, a watchdog function and an 8-bit Input Capture register. 11.3.2 Main features ● Real-time clock – One 8-bit upcounter timebase period (@ 8 MHz f – ...

Page 110

... LTICR REGISTER 110/245 /32. An overflow event occurs when the OSC = 8 MHz, then the time period between two OSC 4µ MHz f ) OSC 01h 02h 03h 04h xxh ST7LITE49K2 /32 starting from the value OSC CLEARED BY S/W READING 05h 06h 07h LTIC REGISTER 07h 04h t ...

Page 111

... ST7LITE49K2 11.3.4 Low power modes Table 39. Effect of low power modes on Lite timer 2 Mode Slow Wait Active-halt Halt 11.3.5 Interrupts Table 40. Description of interrupt events Interrupt Event Timebase 1 Event Timebase 2 Event IC Event The TBxF and ICF interrupt events are connected to the same interrupt vector (see Section 8: Interrupts) ...

Page 112

... Bit 7 = ICIE Interrupt enable bit This bit is set and cleared by software. 0: Input Capture (IC) interrupt disabled 1: Input Capture (IC) interrupt enabled 112/245 AR5 AR4 AR3 Read / Write CNT5 CNT4 CNT3 Read only TB TB1IE TB1F Read / Write ST7LITE49K2 0 AR2 AR1 AR0 0 CNT2 CNT1 CNT0 0 ...

Page 113

... ST7LITE49K2 Bit 6 = ICF Input capture flag This bit is set by hardware and cleared by software by reading the LTICR register. Writing to this bit does not change the bit value Input Capture 1: An Input Capture has occurred Note: After an MCU reset, software must initialize the ICF bit by reading the LTICR register Bit Timebase period selection bit This bit is set and cleared by software ...

Page 114

... On-chip peripherals Table 41. Lite timer register mapping and reset values Address Register 7 label (Hex.) LTCSR1 ICIE 0F Reset Value 0 LTICR ICR7 10 Reset Value 0 114/245 ICF TB TB1IE TB1F ICR6 ICR5 ICR4 ST7LITE49K2 ICR3 ICR2 ICR1 ICR0 0 ...

Page 115

... ST7LITE49K2 11.4 16-bit timer 11.4.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input signals (input capture) or generation two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler ...

Page 116

... The value in the counter register repeats every 131 072, 262 144 or 524 288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can external frequency. CPU 116/245 (see16-bit read sequence (from either the counter register or the 118). ST7LITE49K2 /2, f /4, CPU CPU ...

Page 117

... Low high Input Input Output capture capture compare register 1 register 2 register 2 16 Edge detect circuit 1 Edge detect circuit 2 LATCH1 LATCH2 OC2E OPM PWM CC1 CC0 IEDG2 CR 2 (control register 2) Table 18: ST7LITE49K2 16 ICAP1 pin ICAP2 pin OCMP1 pin OCMP2 pin EXEDG 117/245 ...

Page 118

... EXTCLK that triggers the free running counter. The counter is synchronized with the falling edge of the internal CPU clock. 118/245 Beginning of the sequence Read MSB At t0 Other instructions Read LSB At t0 +Δt Sequence completed ST7LITE49K2 LSB is buffered Returns the buffered LSB value at t0 ...

Page 119

... ST7LITE49K2 A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency. Figure 57. Counter timing diagram, internal clock divided by 2 Timer overflow flag (TOF) Figure 58 ...

Page 120

... The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any transitions on these pins activate the input capture function. Moreover if one of the ICAPi pin is configured as an input and the second one as an output, an interrupt can be generated if 120/245 MSB ICiHR Figure 61). ST7LITE49K2 LSB ICiLR CC[1:0]). f / CPU ...

Page 121

... ST7LITE49K2 the user toggle the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6 The TOF bit can be used with interrupt in order to measure event that go beyond the timer range (FFFFh) ...

Page 122

... The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). ● A timer interrupt is generated if the OCIE bit is set in the CR2 register and the I bit is cleared in the CC register (CC). 122/245 MSB OCiHR R value to 8000h Timer A control register 2 (TACR2) on page ST7LITE49K2 LSB OCiLR ). f CPU/ CC[1:0] 132). ...

Page 123

... ST7LITE49K2 The OC R register value required for a specific timing application can be calculated using i the following formula: Equation 1 Where: Δ output compare period (in seconds CPU clock frequency (in hertz) CPU = timer prescaler factor ( depending on CC[1:0] bits, see PRESC register 2 (TACR2) on page If the timer clock is an external clock, the formula is: Equation 2 Δ ...

Page 124

... OC1E CC1 OC2E CR2 (control register 2) CR1 (control register 1) FOLV2 FOLV1 OCIE OLVL2 OCF1 OCF2 = f TIMER CPU Timer clock 2ECF 2ED0 2ED1 Counter register ST7LITE49K2 CC0 OLVL1 Latch 1 Latch (status register) /2 2ED2 2ED4 2ED3 2ED3 OCMP1 pin OCMP2 ...

Page 125

... ST7LITE49K2 Figure 64. Output compare timing diagram, f Output compare register i (OCRi) Output compare flag i (OCFi) One pulse mode One pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the input capture1 function and the output compare1 function. ...

Page 126

... OLVL1 bit is output on the OCMP1 pin, (see 126/245 One pulse mode cycle When event occurs on ICAP1 When counter = OC1R t OCiR value = PRESC 132 EXT Figure ST7LITE49K2 ICR1 = counter OCMP1 = OLVL2 to FFFCh Counter is reset ICF1 bit is set OCMP1 = OLVL1 CPU 66). : Timer A ...

Page 127

... ST7LITE49K2 Note: 1 The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an output compare interrupt. 2 When the pulse width modulation (PWM) and one pulse mode (OPM) bits are both set, the PWM mode is the only active one. ...

Page 128

... OC2R and OC1R registers. If OLVL1 = OLVL2 a continuous signal is seen on the OCMP1 pin. 128/245 Equation 5. (see: Timer A control register 2 (TACR2) on page Pulse width modulation cycle When counter OCMP1 = OLVL1 = OC1R OCMP1 = OLVL2 When counter Counter is reset = OC2R to FFFCh ICF1 bit is set ST7LITE49K2 132). ...

Page 129

... ST7LITE49K2 The OC R register value required for a specific timing application can be calculated using i the following formula: Equation 5 Where signal or pulse period (in seconds CPU clock frequency (in hertz) CPU = timer prescaler factor ( depending on CC[1:0] bits, see PRESC register 2 (TACR2) on page If the timer clock is an external clock the formula is: ...

Page 130

... See note 4 in Pulse width modulation mode on page 130/245 Interrupt event Input capture 1 (2) Yes (2) and/or Yes No Not recommended No Not recommended 125. 125. 127. ST7LITE49K2 (1) Event Enable Exit from flag control bit Wait ICF1 Yes ICIE ICF2 Yes OCF1 Yes OCIE OCF2 Yes ...

Page 131

... ST7LITE49K2 11.4.7 16-bit timer registers Each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. TIMA control register 1 (TACR1) Reset value: 0000 0000 (00h) ...

Page 132

... OC1R register; the period depends on the value of OC2R register. Bits 3:2 CC[1:0] Clock control The timer clock mode depends on the following bits: 00: Timer clock = f 01: Timer clock = f 132/245 OPM PWM Read / Write /4 CPU /2 CPU ST7LITE49K2 CC[1:0] IEDG2 EXEDG 0 ...

Page 133

... ST7LITE49K2 10: Timer clock = f 11: Timer clock = external clock (where available) Note: If the external clock pin is not available, programming the external clock configuration stops the counter. Bit 1 = IEDG2 Input edge 2 This bit determines which type of level transition on the ICAP2 pin triggers the capture. ...

Page 134

... MSB Timer A input capture 1 low register (TAIC1LR) Reset value: undefined This is an 8-bit read-only register that contains the low part of the counter value (transferred by the input capture 1 event). 7 MSB 134/245 Read Only Read Only ST7LITE49K2 0 LSB 0 LSB ...

Page 135

... ST7LITE49K2 Timer A output compare 1 high register (TAOC1HR) Reset value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB Timer A output compare 1 low register (TAOC1LR) Reset value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register ...

Page 136

... This is an 8-bit read-only register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the CSR register. 7 MSB 136/245 Read Only Read Only Read Only Read Only ST7LITE49K2 0 LSB 0 LSB 0 LSB 0 LSB ...

Page 137

... ST7LITE49K2 Input capture 2 high register (IC2HR) Reset value: undefined This is an 8-bit read-only register that contains the high part of the counter value (transferred by the input capture 2 event). 7 MSB Input capture 2 low register (IC2LR) Reset value: undefined This is an 8-bit read-only register that contains the low part of the counter value (transferred by the input capture 2 event) ...

Page 138

... Reset value TAICHR2 60 Reset value TAICLR2 61 Reset value TAOCHR2 62 Reset value TAOCLR2 63 Reset value 138/245 MSB MSB MSB - - - - MSB - - - - MSB - - - - MSB - - - - ST7LITE49K2 LSB LSB LSB - - - - LSB - - - - LSB - - - - LSB - - - - ...

Page 139

... ST7LITE49K2 2 11 bus interface (I 11.5.1 Introduction 2 The I C Bus Interface serves as an interface between the microcontroller and the serial I bus. It provides both multimaster and slave functions, and controls all I sequencing, protocol, arbitration and timing. It supports fast I 11.5.2 Main features ● Parallel-bus/I ● Multi-master capability ● ...

Page 140

... Data register. The SCL frequency (F 2 the I C bus mode. 140/245 MSB interface may be selected between Standard (up to 100 kHz) and Fast ) is controlled by a programmable clock divider which depends on scl ST7LITE49K2 Figure 69. ACK 8 9 STOP CONDITION ...

Page 141

... ST7LITE49K2 2 When the I C cell is enabled, the SDA and SCL ports must be configured as floating inputs. In this case, the value of the external pull-up resistor used depends on the application. 2 When the I C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins. ...

Page 142

... The slave waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see When the acknowledge pulse is received the EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. 142/245 Section 11.5.7. for the bit definitions. Figure 71 Transfer sequencing EV2). Figure 71 Transfer sequencing EV3). ST7LITE49K2 ...

Page 143

... ST7LITE49K2 Closing slave communication After the last data byte is transferred a Stop Condition is generated by the master. The interface detects this condition and sets: EVF and STOPF bits with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR2 register (see EV4) ...

Page 144

... Note: In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte. 144/245 Figure 71 Figure 71 Transfer sequencing EV9). Figure 71 Figure 71 Transfer sequencing EV7). ST7LITE49K2 Transfer sequencing Transfer sequencing ...

Page 145

... ST7LITE49K2 Master transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register. The master waits for a read of the SR1 register followed by a write in the DR register, ...

Page 146

... EV1 EV3 EV3 Data1 A EV6 EV7 Data1 A EV6 EV8 EV8 Address A Data1 EV1 S Header A Data1 A r EV1 EV3 Address A EV9 EV6 EV8 S Header A r EV5 EV6 ST7LITE49K2 A DataN A ..... EV2 EV2 Data NA N .... . EV3- EV3 Data2 A DataN NA .... . EV7 Data Data2 A .... N . EV8 ...

Page 147

... ST7LITE49K2 subsequent EV4 is not seen. 6. EV4: EVF=1, STOPF=1, cleared by reading SR2 register. 7. EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register. 8. EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1). 9. EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. ...

Page 148

... This bit is set and cleared by software also cleared by hardware when the interface is disabled (PE=0 acknowledge returned 1: Acknowledge returned after an address byte or a data byte is received 148/245 PE ENGC START Read / Write 2 C standard, when GCAL addressing is enabled ST7LITE49K2 0 ACK STOP ITE 2 C slave can ...

Page 149

... ST7LITE49K2 Bit 1 = STOP Generation of a Stop condition bit This bit is set and cleared by software also cleared by hardware in master mode. Note: This bit is not cleared when the interface is disabled (PE=0). ● In master mode stop generation 1: Stop generation after the current byte transfer or after the current Start condition is sent. The STOP bit is cleared by hardware when the Stop condition is sent. ● ...

Page 150

... This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition. It indicates a communication in progress on the bus. The BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs communication on the bus 1: Communication ongoing on the bus 150/245 TRA BUSY BTF Read Only ST7LITE49K2 0 ADSL M/SL SB Figure 71 also cleared by ...

Page 151

... ST7LITE49K2 Bit 3 = BTF Byte Transfer Finished bit This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE= cleared by software reading SR1 register followed by a read or write of DR register also cleared by hardware when the interface is disabled (PE=0). ...

Page 152

... An interrupt is generated if ITE= cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while BERR= misplaced Start or Stop condition 1: Misplaced Start or Stop condition 152/245 0 AF STOPF Read Only 2 C master does not acknowledge the ST7LITE49K2 0 ARLO BERR GCAL ...

Page 153

... ST7LITE49K2 Note Bus Error occurs, a Stop or a repeated Start condition should be generated by the Master to re-synchronize communication, get the transmission acknowledged and the bus released for further communication Bit 0 = GCAL General Call bit (slave mode). This bit is set by hardware when a general call address is detected on the bus while ENGC=1 ...

Page 154

... Read / Write 2 C specified delays select the value corresponding to the . CPU 2 C delay times f CPU < 6 MHz MHz 2 C bus address of the interface (10-bit mode ST7LITE49K2 ADD3 ADD2 ADD1 2 C bus address of the 0 ADD9 ADD8 FR1 FR0 ADD0 ...

Page 155

... ST7LITE49K2 2 Table 49 register mapping and reset values Address Register 7 label (Hex.) I2CCR 0064h Reset 0 Value I2CSR1 EVF 0065h Reset 0 Value I2CSR2 0066h Reset 0 Value I2CCCR FM/SM 0067h Reset 0 Value I2COAR1 ADD7 0068h Reset 0 Value I2COAR2 FR1 0069h Reset 0 Value I2CDR MSB ...

Page 156

... SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS inputs can be driven by standard I/O ports on the master Device. 156/245 /4 max.) CPU shows the serial peripheral interface (SPI) block diagram. There are ST7LITE49K2 ...

Page 157

... ST7LITE49K2 Figure 73. Serial peripheral interface block diagram SPIDR Read Buffer MOSI MISO 8-Bit Shift Register SOD bit SCK SS 11.6.4 Functional description A basic example of interconnections between a single master and a single slave is illustrated in Figure The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first) ...

Page 158

... Collision error will occur when the slave writes to the shift register (see collision error 158/245 LSBit MISO MOSI SCK SS +5V Figure 76). (WCOL)). ST7LITE49K2 SLAVE MSBit MISO 8-BIT SHIFT REGISTER MOSI SCK SS Not used managed by software Figure , or made free for standard I/O by ...

Page 159

... ST7LITE49K2 Figure 75. Generic SS timing diagram MOSI/MISO Master SS Slave SS (if CPHA = 0) Slave SS (if CPHA = 1) Figure 76. Hardware/software slave select management Master mode operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). ...

Page 160

... An access to the SPICSR register while the SPIF bit is set 2. A write or a read to the SPIDR register Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. 160/245 77). Section : Slave select management ST7LITE49K2 and ...

Page 161

... ST7LITE49K2 The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see condition (OVR)). 11.6.5 Clock phase and clock polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA ...

Page 162

... The MSTR bit is reset, thus forcing the device into slave mode. Clearing the MODF bit is done through a software sequence: 162/245 CPHA = 1 Bit 4 Bit3 Bit 6 Bit 5 Bit 4 Bit3 Bit 6 Bit 5 CPHA = 0 Bit 4 Bit3 Bit 6 Bit 5 Bit 4 Bit3 Bit 6 Bit 5 ST7LITE49K2 Bit 2 Bit 1 LSBit Bit 2 Bit 1 LSBit Bit 2 Bit 1 LSBit Bit 2 Bit 1 LSBit ...

Page 163

... ST7LITE49K2 1. A read access to the SPICSR register while the MODF bit is set write to the SPICR register. Note: To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence ...

Page 164

... The multimaster system is principally handled by the MSTR bit in the SPICR register and the MODF bit in the SPICSR register. 164/245 RESULT SPIF = 0 WCOL = 0 Read SPICSR RESULT Read SPIDR WCOL = 0 Figure 79). ST7LITE49K2 Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit ...

Page 165

... ST7LITE49K2 Figure 79. Single master / multiple slave configuration SCK MOSI MOSI SCK 5V SS 11.6.7 Low power modes Table 50. Low power mode descriptions Mode Wait Halt 11.6.8 Interrupts Table 51. Interrupt events Interrupt event SPI End of Transfer Event Master Mode Fault Event Overrun Error Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). ...

Page 166

... If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. 166/245 SPR2 MSTR CPOL Read / Write Section : Master mode fault (MODF)). The SPE bit is cleared by Table 52: SPI Master mode SCK Section : Master mode fault (MODF)). ST7LITE49K2 0 CPHA SPR1 SPR0 Frequency. ...

Page 167

... ST7LITE49K2 Bit 2 = CPHA Clock phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. The slave must have the same CPOL and CPHA settings as the master. Bits 1:0 = SPR[1:0] Serial clock frequency. ...

Page 168

... This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode) 0: SPI output enabled (if SPE = 1) 1: SPI output disabled 168/245 OVR MODF - Read / Write (some bits Read only) ST7LITE49K2 0 SOD SSM SSI ...

Page 169

... ST7LITE49K2 Bit 1 = SSM SS management. This bit is set and cleared by software. When set, it disables the alternate function of the SPI SS pin and uses the SSI bit value instead. See Section Slave select management. 0: Hardware management (SS managed by external pin) 1: Software management (internal SS signal controlled by SSI bit. External SS pin free for general-purpose I/O) Bit 0 = SSI SS internal Mode ...

Page 170

... Reset Value SPICR 71 Reset Value SPICSR 72 Reset Value 170/245 MSB SPIE SPE SPR2 MSTR SPIF WCOL OVR MODF ST7LITE49K2 LSB CPOL CPHA SPR1 SPR0 SOD SSM SSI ...

Page 171

... ST7LITE49K2 11.7 10-bit A/D converter (ADC) 11.7.1 Introduction The on-chip analog to digital converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from different sources. ...

Page 172

... On-chip peripherals Figure 80. ST7LITE49K2 ADC block diagram f CPU AIN0 AIN1 AINx Digital A/D conversion result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (V conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication) ...

Page 173

... ST7LITE49K2 Configuring the A/D conversion The analog input ports must be configured as input, no pull-up, no interrupt (see I/O ports). Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. To assign the analog channel to convert, select the CH[2:0] bits in the ADCCSR register. ...

Page 174

... The number of channels is device dependent. Refer to the device pinout description. 174/245 ADON 0 Read/write (1) CH3 AIN0 0 AIN1 0 AIN2 0 AIN3 0 AIN4 0 AIN5 0 AIN6 0 AIN7 0 AIN8 1 AIN9 1 ST7LITE49K2 CH3 CH2 CH1 CH2 CH1 CH0 ...

Page 175

... ST7LITE49K2 Data register high (ADCDRH) Reset value: xxxx xxxx (xxh Bits 7:0 = D[9:2] MSB of Analog Converted Value ADC control/data register low (ADCDRL) Reset value: 0000 00xx (0xh Bits 7:5 = Reserved. Forced by hardware to 0. Bit 4 = AMPCAL Amplifier calibration bit This bit is set and cleared by software advised to use this bit to calibrate the ADC when amplifier is ON ...

Page 176

... Reset Value ADCDRL 0038h Reset Value 176/245 EOC SPEED ADON AMPCAL ST7LITE49K2 CH3 CH2 CH1 CH0 SLOW AMPSEL ...

Page 177

... ST7LITE49K2 11.8 Analog comparator (CMP) 11.8.1 Introduction The CMP block consists of two analog comparators (CMPA and CMPB) and an internal voltage reference. The voltage reference can be external or internal, selectable under program control. The comparator input pins COMPIN+ and COMPIN- are also connected to the A/D converter (ADC). ...

Page 178

... COMPINA+ 1.2V Bandgap COMPINA- COMPINB+ COMPINB- 178/245 Section 11.2: Dual 12-bit autoreload timer on page Voltage Reference VR[3:0] bits VCBGR bit VCEXT bit 0 1 VCEXTB bit ST7LITE49K2 Table 59 on 84) Comparator COMPA + - Break 1 input to 12-bit Autoreload Timer Break 2 input to 12-bit Autoreload Timer Comparator COMPB + ...

Page 179

... ST7LITE49K2 Figure 82. Analog comparator Comparator + - CHYST CMPxCR 11.8.4 Register description Internal voltage reference register (VREFCR) Reset Value: 0000 0000 (00h) 7 VCEXT VCBGR Bit 7 = VCEXT External voltage reference for comparators This bit is set or cleared by software used to connect the external reference voltage to the VN comparator inputs. ...

Page 180

... VR0 VN voltage bit bit x x VEXT x x 1.2 bandgap 0.2 V ST7LITE49K2 ...

Page 181

... ST7LITE49K2 Comparator control register (CMPxCR) Reset Value: 1000 0000 (80h) 7 CHYST Bit 7 = CHYST Comparator hysteresis enable This bit is set or cleared by software and set by hardware reset. When this bit is set, the comparator hysteresis is enabled. 0: Hysteresis disabled 1: Hysteresis enabled Note: To avoid spurious toggling of the output of the comparator due to noise on the voltage reference recommended to enable the hysteresis ...

Page 182

... Reset value CMPBCR 0054h Reset value 182/245 Section 13: Electrical characteristics on page VCEXT VCBGR VR3 CINV CHYST CINV CHYST ST7LITE49K2 192 VR2 VR1 VCEXTB VR0 CMPIF CMPIE CMP COUT CMPIF CMPIE CMP COUT 0 ...

Page 183

... ST7LITE49K2 12 Instruction set 12.1 ST7 addressing modes The ST7 core features 17 different addressing modes which can be classified in seven main groups: Table 61. Description of addressing modes Addressing mode The ST7 instruction set is designed to minimize the number of bytes required per instruction so, most of the addressing modes may be subdivided in two submodes called long and short: ● ...

Page 184

... Instruction NOP TRAP WFI HALT RET IRET SIM RIM SCF RCF RSP LD CLR PUSH/POP INC/DEC TNZ CPL, NEG ST7LITE49K2 Pointer Pointer address size 00..FF word (1) 00..FF byte (1) 00..FF byte 00..FF byte Function No operation S/W interrupt Wait for interrupt (low power mode) Halt oscillator (lowest power mode) ...

Page 185

... ST7LITE49K2 Table 63. Instructions supporting inherent addressing mode (continued) SLL, SRL, SRA, RLC, RRC 12.1.2 Immediate mode Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. Imm Table 64. Instructions supporting inherent immediate addressing mode Immediate instruction ...

Page 186

... Table 65. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes Long and short instructions AND, OR, XOR ADC, ADD, SUB, SBC 186/245 Instructions LD CP BCP ST7LITE49K2 Function Load Compare Logical operations Arithmetic addition/subtraction operations Bit compare ...

Page 187

... ST7LITE49K2 Table 65. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes (continued) Short instructions only SLL, SRL, SRA, RLC, RRC 12.1.7 Relative modes (direct, indirect) This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it. Table 66. Instructions supporting relative modes ...

Page 188

... INC DEC CP TNZ BCP AND OR XOR CPL BSET BRES BTJT BTJF ADC ADD SUB SBC SLL SRL SRA RLC JRA JRT JRF JP JRxx TRAP WFI HALT IRET SIM RIM SCF RCF ST7LITE49K2 NEG MUL RRC SWAP SLA CALL CALLR NOP RET ...

Page 189

... ST7LITE49K2 12.2.1 Illegal opcode reset In order to provide enhanced robustness to the device against unexpected behavior, a system of illegal opcode detection is implemented: a reset is generated if the code to be executed does not correspond to any opcode or prebyte value. This, combined with the Watchdog, allows the detection and recovery from an unexpected fault or interference. ...

Page 190

... S = Max allowed <= Dst <= 0 reg <= Dst <= 0 reg => Dst => C reg, M Dst7 => Dst => C reg Dst[7..4]<=>Dst[3..0] reg, M tnz lbl1 S/W interrupt ST7LITE49K2 Src reg ...

Page 191

... ST7LITE49K2 Table 68. Illegal opcode detection (continued) Mnemo Description WFI Wait for Interrupt XOR Exclusive OR Function/Example Dst XOR M A Instruction set Src 191/245 C ...

Page 192

... Figure 83. Pin loading conditions 13.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in 192/245 . °C and ° 3.3 V (for the 3.0 V≤V DD ST7 PIN C L ST7LITE49K2 = T max (given (for the DD ≤3.6 V voltage range). DD Figure 83. Figure 84. ...

Page 193

... ST7LITE49K2 Figure 84. Pin input voltage 13.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability ...

Page 194

... SS >V while a negative injection is induced maximum current injection on four I/O port pins of the device. INJ(PIN) Ratings Storage temperature range Maximum junction temperature (see ST7LITE49K2 Maximum value (1) 75 (1) 150 ± 5 ± 5 (4) ± 5 ± ...

Page 195

... ST7LITE49K2 13.3 Operating conditions 13.3.1 General operating conditions T = -40 to +125 °C unless otherwise specified. A Table 72. General operating conditions Symbol CPU clock frequency CPU Figure 85. f CPU f CPU FUNCTIONALITY NOT GUARANTEED IN THIS AREA 13.3.2 Operating conditions with low voltage detector (LVD -40 to 125 °C unless otherwise specified. ...

Page 196

... Not tested in production, guaranteed by characterization. 196/245 Parameter Conditions High Threshold Med. Threshold rise) DD Low Threshold High Threshold Med. Threshold fall) DD Low Threshold V IT+ (AVD) hysteresis supply. Min 800 1400 600 100 950 250 1600 900 ST7LITE49K2 (1) (2) (2) Min Typ Max 4.0 4.4 4.8 3.4 3.7 4.1 2.6 2.9 3.2 3.9 4.3 4.7 3.3 3.6 4.0 2.5 2.8 3.1 -V 150 IT- ...

Page 197

... ST7LITE49K2 13.3.5 Internal RC oscillator To improve clock stability and frequency accuracy recommended to place a decoupling capacitor, typically 100 nF, between the V device Internal RC oscillator calibrated at 5.0 V The ST7 internal clock can be supplied by an internal RC oscillator (selectable by option byte). Table 76. Internal RC oscillator characteristics (5.0 V calibration) Symbol ...

Page 198

... V = 3 ° 3 ° 3 .200 8 .160 8 .120 8 .080 8 .040 8 .000 7 .960 7 .920 7 .880 7 .840 7 .800 VDD (V) ST7LITE49K2 Min Typ Max 4.3 7.84 8 8. (3) -2 (4) -4 2.5 ( 5V@- 40 °C RC 5V@25 °C RC 5V@85 °C RC 5V@12 5 ° ...

Page 199

... ST7LITE49K2 Figure 87. Frequency vs voltage at four different ambient temperatures (RC at 3.3 V) Figure 88. Accuracy voltage at 4 different ambient temperatures ( Figure 89. Accuracy voltage at 4 different ambient temperatures (RC at 3.3V) 8 .240 8 .200 8 .160 8 .120 8 .080 8 .040 8 .000 7 .960 7 .920 7 .880 7 .840 3.6 4 ...

Page 200

... All I/O pins in input mode with a static value at V OSC based on f divided by 32. All I/O pins in input mode with a static value at V OSC or V (no load). Data tested in production (no load), LVD disabled. Data based on characterization results, SS max. CPU ST7LITE49K2 Typ Max = 4 MHz 2.8 4 MHz 5 MHz 1.5 2 MHz 2.7 ...