ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 106

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

On-chip peripherals
Note:
Note:
106/245
1
2
1
2
3
Bit 1= TRAN2 Transfer enable2 bit
DCR2/3 transfer will be controlled using this bit if ENCNTR2 bit is set.
This bit must not be reset by software
Bit 0 = TRAN1 Transfer enable 1 bit
DCR0,1 transfers are always controlled using this bit.
DCR2/3 transfer will be controlled using this bit if ENCNTR2 is reset.
This bit must not be reset by software
Autoreload register 2 (ATR2H)
Reset value: 0000 0000 (00h)
Autoreload register (ATR2L)
Reset value: 0000 0000 (00h)
Bits 11:0 = ATR2[11:0] Autoreload register 2
This is a 12-bit register which is written by software. The ATR2 register value is
automatically loaded into the upcounter CNTR2 when an overflow of CNTR2 occurs. The
register value is used to set the PWM2/PWM3 frequency when ENCNTR2 is set.
ATR7
This bit is read/write by software, cleared by hardware after each completed transfer
and set by hardware after reset. It controls the transfers on CNTR2.
It allows the value of the Preload DCRx registers to be transferred to the Active DCRx
registers after the next overflow event.
The OPx bits are transferred to the shadow OPx bits in the same way.
This bit is read/write by software, cleared by hardware after each completed transfer
and set by hardware after reset. It controls the transfers on CNTR1. It allows the value
of the Preload DCRx registers to be transferred to the Active DCRx registers after the
next overflow event.
The OPx bits are transferred to the shadow OPx bits in the same way.
15
0
7
ATR6
0
ATR5
0
ATR4
0
Read/write
Read/write
ATR11
ATR3
ATR10
ATR2
ATR9
ATR1
ST7LITE49K2
ATR0
ATR8
0
8