ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 160

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

On-chip peripherals
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Master mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
●
●
Clearing the SPIF bit is performed by the following software sequence:
1.
2.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Slave mode operation
In slave mode, the serial clock is received on the SCK pin from the master device.
To operate the SPI in slave mode:
1.
The slave must have the same CPOL and CPHA settings as the master.
2.
Slave mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin.
When data transfer is complete:
●
●
Clearing the SPIF bit is performed by the following software sequence:
1.
2.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
The SPIF bit is set by hardware.
An interrupt request is generated if the SPIE bit is set and the interrupt mask in the
CCR register is cleared.
An access to the SPICSR register while the SPIF bit is set
A read to the SPIDR register
Write to the SPICSR register to perform the following actions:
–
–
Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI
I/O functions.
The SPIF bit is set by hardware.
An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR
register is cleared.
An access to the SPICSR register while the SPIF bit is set
A write or a read to the SPIDR register
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits
(see
Manage the SS pin as described in
Figure
held low during byte transmission and pulled up between each byte to let the slave
write in the shift register.
Figure
75. If CPHA = 1 SS must be held low continuously. If CPHA = 0 SS must be
77).
Section : Slave select management
ST7LITE49K2
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