ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 101

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

ST7LITE49K2
PWMX control status register (PWMxCSR)
Reset value: 0000 0000 (00h)
Bits 7:4= Reserved, must be kept cleared.
Bit 3 = OP_EN One Pulse Mode Enable bit
Bit 2 = OPEDGE One Pulse Edge Selection bit
Bit 1 = OPx PWMx Output Polarity bit
Bit 0 = CMPFx PWMx Compare flag
Break control register 1 (BREAKCR)
Reset value: 0000 0000 (00h)
Bit 7 = BR1SEL Break 1 input selection bit
BR1SEL
This bit is read/write by software and cleared by hardware after a reset. This bit enables
the One Pulse feature for PWM2 and PWM3 (only available for PWM3CSR)
0: One Pulse mode disable for PWM2/3.
1: One Pulse mode enable for PWM2/3.
This bit is read/write by software and cleared by hardware after a reset. This bit selects
the polarity of the LTIC signal for One Pulse feature. This bit will be effective only if
OP_EN bit is set (only available for PWM3CSR)
0: Falling edge of LTIC is selected.
1: Rising edge of LTIC is selected.
This bit is read/write by software and cleared by hardware after a reset. This bit selects
the polarity of the PWM signal.
0: The PWM signal is not inverted.
1: The PWM signal is inverted.
This bit is set by hardware and cleared by software by reading the PWMxCSR register.
It indicates that the upcounter value matches the Active DCRx register value.
0: Upcounter value does not match DCRx value.
1: Upcounter value matches DCRx value.
This bit is read/write by software and cleared by hardware after reset. It selects the
active Break 1 signal from external BREAK1 pin and the output of the comparator.
0: External BREAK1 pin is selected for break mode.
1: Comparator 1 output is selected for break mode.
7
0
7
BR1EDGE
0
BA1
0
BP1EN
0
Read/write
Read/write
OP_EN
PWM3
OPEDGE
PWM2
On-chip peripherals
OPx
PWM1
CMPFx
PWM0
101/245
0
0