ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 150

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

On-chip peripherals
150/245
I
Reset value: 0000 0000 (00h)
Bit 7 = EVF Event flag
Bit 6 = ADD10 10-bit addressing in Master mode
Bit 5 = TRA Transmitter/Receiver bit
Bit 4 = BUSY Bus busy bit
2
C status register 1 (I2CSR1)
EVF
This bit is set by hardware as soon as an event occurs. It is cleared by software reading
SR2 register in case of error event or as described in
hardware when the interface is disabled (PE=0).
0: No event
1: One of the following events has occurred:
–
–
–
–
–
–
–
–
–
This bit is set by hardware when the master has sent the first byte in 10-bit address
mode. It is cleared by software reading SR2 register followed by a write in the DR
register of the second address byte. It is also cleared by hardware when the peripheral
is disabled (PE=0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically
when BTF is cleared. It is also cleared by hardware after detection of Stop condition
(STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
This bit is set by hardware on detection of a Start condition and cleared by hardware on
detection of a Stop condition. It indicates a communication in progress on the bus. The
BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs.
0: No communication on the bus
1: Communication ongoing on the bus
7
BTF=1 (byte received or transmitted)
ADSL=1 (Address matched in Slave mode while ACK=1)
SB=1 (Start condition generated in Master mode)
AF=1 (No acknowledge received after byte transmission)
STOPF=1 (Stop condition detected in Slave mode)
ARLO=1 (Arbitration lost in Master mode)
BERR=1 (Bus error, misplaced Start or Stop condition detected)
ADD10=1 (Master has sent header byte)
Address byte successfully transmitted in Master mode.
ADD10
TRA
BUSY
Read Only
BTF
Figure
ADSL
71. It is also cleared by
M/SL
ST7LITE49K2
SB
0