ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 35

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

ST7LITE49K2
Note:
Bit 3 = I Interrupt mask bit
Interrupts requested while I is set are latched and can be processed when I is cleared. By
default an interrupt routine is not interruptible because the I bit is set by hardware at the start
of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared
by software in the interrupt routine, pending interrupts are serviced regardless of the priority
level of the current interrupt routine.
Bit 2 = N Negative bit
Bit 1 = Z Zero bit
Bit 0 = C Carry/borrow bit
Interrupt management bits
Bits 5,3 = I1, I0 Interrupt bits
This bit is set by hardware when entering in interrupt or by software to disable all
interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM
and JRNM instructions.
This bit is set and cleared by hardware. It is representative of the result sign of the last
arithmetic, logical or data manipulation. It is a copy of the 7
0: The result of the last operation is positive or null.
1: The result of the last operation is negative (that is, the most significant bit is a logic
1).
This bit is accessed by the JRMI and JRPL instructions.
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
The combination of the I1 and I0 bits gives the current interrupt software priority.
These two bits are set/cleared by hardware when entering in interrupt. The loaded
value is given by the corresponding bits in the interrupt software priority registers
(IxSPR). They can be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI
and PUSH/POP instructions. See
Section 10.6: Interrupts
for more details.
th
bit of the result.
Central processing unit
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