ST72651AR6 STMicroelectronics, ST72651AR6 Datasheet - Page 27

• Manufacturer Part Number: ST72651AR6
• Description: LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI
• Manufacturer: STMicroelectronics

Specifications of ST72651AR6

• Dual Supply Management: analog voltage detector on the USB power line to enable smart power switching from USB power to battery (on E suffix devices).
• Programmable Internal Voltage Regulator For Memory Cards (2.8v To 3.5v) Supplying: Flash Card I/O lines (voltage shifting)
• 5 Usb Endpoints: 1 control endpoint
• Dtc (data Transfer Coprocessor): Universal Serial/Parallel communications interface, with software plug-ins for current and future protocol standards

6.2 RESET SEQUENCE MANAGER (RSM)
6.2.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in
■
■
■
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
Figure 17. RESET Sequences
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
WATCHDOG
RESET
EXTERNAL
RESET
SOURCE
RESET PIN
V
V
IT+(LVD)
IT-(LVD)
RUN
V
DD
ACTIVE PHASE
Figure
RESET
LVD
6.2.2:
t
t
w(RSTL)out
h(RSTL)in
RUN
Doc ID 7215 Rev 4
ACTIVE
PHASE
SHORT EXT.
RESET
DELAY
The basic RESET sequence consists of 3 phases
as shown in
■
■
■
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed. For this reason, it is recom-
mended to keep the RESET pin in low state until
programming mode is entered, in order to avoid
unwanted behaviour.
t
Active Phase depending on the RESET source
Min 512 CPU clock cycle delay (see
and
RESET vector fetch
h(RSTL)in
t
w(RSTL)out
RUN
Figure 20
WATCHDOG UNDERFLOW
Figure
ACTIVE
PHASE
LONG EXT.
RESET
17:
INTERNAL RESET (min 512 T
VECTOR FETCH
RUN
ACTIVE
PHASE
WATCHDOG
ST72651AR6
RESET
t
w(RSTL)out
Figure 19
RUN
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CPU
)
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