ST72651AR6 STMicroelectronics, ST72651AR6 Datasheet - Page 76

• Manufacturer Part Number: ST72651AR6
• Description: LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI
• Manufacturer: STMicroelectronics

Specifications of ST72651AR6

• Dual Supply Management: analog voltage detector on the USB power line to enable smart power switching from USB power to battery (on E suffix devices).
• Programmable Internal Voltage Regulator For Memory Cards (2.8v To 3.5v) Supplying: Flash Card I/O lines (voltage shifting)
• 5 Usb Endpoints: 1 control endpoint
• Dtc (data Transfer Coprocessor): Universal Serial/Parallel communications interface, with software plug-ins for current and future protocol standards

ST72651AR6
11.4 16-BIT TIMER
11.4.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
11.4.2 Main Features
■
■
■
■
The Block Diagram is shown in
76/161
1
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
Programmable prescaler: f
Overflow status flag and maskable interrupt
Output compare functions with
2 alternate functions on I/O ports (OCMP1,
OCMP2)
CPU
divided by 2, 4 or 8.
Figure
41.
Doc ID 7215 Rev 4
11.4.3 Functional Description
11.4.3.1 Counter
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
Counter Register (CR):
Alternate Counter Register (ACR)
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er).
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in
Control
peats every 131.072, 262.144 or 524.288 CPU
clock cycles depending on the CC[1:0] bits.
The timer frequency can be f
or an external frequency.
– Counter High Register (CHR) is the most sig-
– Counter Low Register (CLR) is the least sig-
– Alternate Counter High Register (ACHR) is the
– Alternate Counter Low Register (ACLR) is the
nificant byte (MS Byte).
nificant byte (LS Byte).
m ost significant byte (MS Byte).
least significant byte (LS Byte ).
Bits. The value in the counter register re-
CPU
/2, f
Table 27 Clock
CPU
/4, f
CPU
/8