ST72651AR6 STMicroelectronics, ST72651AR6 Datasheet - Page 71

• Manufacturer Part Number: ST72651AR6
• Description: LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI
• Manufacturer: STMicroelectronics

Specifications of ST72651AR6

• Dual Supply Management: analog voltage detector on the USB power line to enable smart power switching from USB power to battery (on E suffix devices).
• Programmable Internal Voltage Regulator For Memory Cards (2.8v To 3.5v) Supplying: Flash Card I/O lines (voltage shifting)
• 5 Usb Endpoints: 1 control endpoint
• Dtc (data Transfer Coprocessor): Universal Serial/Parallel communications interface, with software plug-ins for current and future protocol standards

USB INTERFACE (Cont’d)
Bits 1:0 = STAT_RX [1:0] Status bits, for reception
transfers.
These bits contain the information about the end-
point status, as listed below:
Table 21. Reception Status Encoding
These bits are written by software. Hardware sets
the STAT_RX and STAT_TX bits to NAK when a
correct transfer has occurred (CTR=1) addressed
to this endpoint, so the software has the time to ex-
amine the received data before acknowledging a
new transaction.
Notes:
If a SETUP is received while the status is other
than DISABLED, it is acknowledged and the two
directional status bits are set to NAK by hardware.
When a STALL is answered by the USB device,
the two directional status bits are set to STALL by
hardware.
ENDPOINT
(EP1RXR)
Read/Write
Reset value: 0000 0000 (00h)
STAT_RX1 STAT_RX0
7
0
0
0
1
1
0
0
1
0
1
0
1
RECEPTION
0
DISABLED: no function can be
executed on this endpoint and
messages related to this end-
point are ignored.
STALL: the endpoint is stalled
and all reception requests re-
sult in a STALL handshake.
NAK: the endpoint is NAKed
and all reception requests re-
sult in a NAK handshake.
VALID: this endpoint is ena-
bled (if an address match oc-
curs, the USB interface
handles the transaction).
CTR_R
X
DTOG
Meaning
_RX
STAT_
REGISTER
RX1
Doc ID 7215 Rev 4
STAT_
RX0
0
This register is used for controlling Endpoint 1 re-
ception. Bits 2:0 are also reset by a USB reset, ei-
ther received from the USB or forced through the
FRES bit in the CTLR register.
Bits 7:4 Reserved, forced by hardware to 0.
Bit 3 = CTR_RX Correct Reception Transfer.
This bit is set by hardware when a correct transfer
operation is performed in reception. This bit must
be cleared after the corresponding interrupt has
been serviced.
Bit 2 = DTOG_RX Data Toggle, for reception
transfers.
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet.
The receiver toggles DTOG_RX only if it receives
a correct data packet and the packet’s data PID
matches the receiver sequence bit.
Bits 1:0 = STAT_RX [1:0] Status bits, for reception
transfers.
These bits contain the information about the end-
point status, as listed below:
Table 22. Reception Status Encoding:
These bits are written by software, but hardware
sets the STAT_RX bits to NAK when a correct
transfer has occurred (CTR=1) addressed to this
endpoint, so the software has the time to examine
the received data before acknowledging a new
transaction.
STAT_RX1 STAT_RX0
0
0
1
1
0
1
0
1
DISABLED: reception trans-
fers cannot be executed.
STALL: the endpoint is stalled
and all reception requests re-
sult in a STALL handshake.
NAK: the endpoint is naked
and all reception requests re-
sult in a NAK handshake.
VALID: this endpoint is ena-
bled for reception.
Meaning
ST72651AR6
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