ST72651AR6 STMicroelectronics, ST72651AR6 Datasheet - Page 55

• Manufacturer Part Number: ST72651AR6
• Description: LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI
• Manufacturer: STMicroelectronics

Specifications of ST72651AR6

• Dual Supply Management: analog voltage detector on the USB power line to enable smart power switching from USB power to battery (on E suffix devices).
• Programmable Internal Voltage Regulator For Memory Cards (2.8v To 3.5v) Supplying: Flash Card I/O lines (voltage shifting)
• 5 Usb Endpoints: 1 control endpoint
• Dtc (data Transfer Coprocessor): Universal Serial/Parallel communications interface, with software plug-ins for current and future protocol standards

WATCHDOG TIMER (Cont’d)
11.1.4 Software Watchdog Option
If Software Watchdog is selected by option byte,
the watchdog is disabled following a reset. Once
activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
11.1.6 Low Power Modes
Recommendations
– Make sure that an external event is available to
– Before executing the HALT instruction, refresh
– When using an external interrupt to wake up the
11.1.7 Interrupts
None.
WAIT
HALT
wake up the microcontroller from Halt mode.
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcon-
troller.
microcontroller, reinitialize the corresponding I/O
as Input before executing the HALT instruction.
The main reason for this is that the I/O may be
wrongly configured due to external interference
or by an unforeseen logical condition.
Mode
If the WDGHALT bit in the MISCR3 register is set, Halt mode can be used when the watchdog
is enabled. When the oscillator is stopped, the WDG stops counting and is no longer able to
generate a reset until the microcontroller receives an external interrupt or a reset.
If an external interrupt is received, the WDG restarts counting after 514 CPU clocks. In the case
of the Software Watchdog option, if a reset is generated, the WDG is disabled (reset state).
Note: In USB mode, and in Suspend mode, a reset is not generated by entering Halt mode
No effect on Watchdog.
Doc ID 7215 Rev 4
Description
11.1.5 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
– The opcode for the HALT instruction is 0x8E. To
– As the HALT instruction clears the I bits in the
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
FLASH with the value 0x8E.
CC register to allow interrupts, the user may
choose to clear all pending interrupt bits before
executing the HALT instruction. This avoids en-
tering other peripheral interrupt routines after ex-
ecuting the external interrupt routine
corresponding to the wake-up event (reset or ex-
ternal interrupt).
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