ST72651AR6 STMicroelectronics, ST72651AR6 Datasheet - Page 70
ST72651AR6
Manufacturer Part Number
ST72651AR6
Description
LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI
Manufacturer
STMicroelectronics
Datasheet
1.ST72651AR6.pdf
(161 pages)
Specifications of ST72651AR6
Dual Supply Management
analog voltage detector on the USB power line to enable smart power switching from USB power to battery (on E suffix devices).
Programmable Internal Voltage Regulator For Memory Cards (2.8v To 3.5v) Supplying
Flash Card I/O lines (voltage shifting)
5 Usb Endpoints
1 control endpoint
Dtc (data Transfer Coprocessor)
Universal Serial/Parallel communications interface, with software plug-ins for current and future protocol standards
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ST72651AR6
USB INTERFACE (Cont’d)
Bits 2:0 = ERR[2:0] Error type.
These bits identify the type of error which oc-
curred:
Note: These bits are set by hardware when an er-
ror interrupt occurs and are reset automatically
when the error bit (ISTR bit 4) is cleared by soft-
ware.
ENDPOINT 0 REGISTER (EP0R)
Read/Write
Reset value: 0000 0000 (00h)
This register is used for controlling Endpoint 0. Bits
6:4 and bits 2:0 are also reset by a USB reset, ei-
ther received from the USB or forced through the
FRES bit in CTLR.
Bit 7 = CTR0 Correct Transfer.
This bit is set by hardware when a correct transfer
operation is performed on Endpoint 0. This bit
must be cleared after the corresponding interrupt
has been serviced.
0: No CTR on Endpoint 0
1: Correct transfer on Endpoint 0
Bit 6 = DTOG_TX Data Toggle, for transmission
transfers.
It contains the required value of the toggle bit
(0=DATA0, 1=DATA1) for the next transmitted
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1
ERR2 ERR1 ERR0
CTR0
0
0
0
0
1
1
1
7
DTOG
_TX
0
0
1
1
0
0
1
STAT_
TX1
0
1
0
1
0
1
1
STAT_
No error
Bitstuffing error
CRC error
EOP error (unexpected end of
packet or SE0 not followed by
J-state)
PID error (PID encoding error,
unexpected or unknown PID)
Memory over / underrun (mem-
ory controller has not an-
swered in time to a memory
data request)
Other error (wrong packet, tim-
eout error)
TX0
0
Meaning
DTOG
_RX
STAT_
RX1
Doc ID 7215 Rev 4
STAT_
RX0
0
data packet. This bit is set by hardware on recep-
tion of a SETUP PID. DTOG_TX toggles only
when the transmitter has received the ACK signal
from the USB host. DTOG_TX and also
DTOG_RX are normally updated by hardware, on
receipt of a relevant PID. They can be also written
by the user, both for testing purposes and to force
a specific (DATA0 or DATA1) token.
Bits 5:4 = STAT_TX [1:0] Status bits, for transmis-
sion transfers.
These bits contain the information about the end-
point status, as listed below:
Table 20. Transmission Status Encoding
These bits are written by software. Hardware sets
the STAT_TX and STAT_RX bits to NAK when a
correct transfer has occurred (CTR=1) addressed
to this endpoint; this allows software to prepare the
next set of data to be transmitted.
Bit 3 = Reserved, forced by hardware to 0.
Bit 2 = DTOG_RX Data Toggle, for reception
transfers.
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet.
This bit is cleared by hardware in the first stage
(Setup Stage) of a control transfer (SETUP trans-
actions start always with DATA0 PID). The receiv-
er toggles DTOG_RX only if it receives a correct
data packet and the packet’s data PID matches
the receiver sequence bit.
STAT_TX1 STAT_TX0
0
0
1
1
0
1
0
1
DISABLED: no function can be
executed on this endpoint and
messages related to this end-
point are ignored.
STALL: the endpoint is stalled
and all transmission requests
result in a STALL handshake.
NAK: the endpoint is NAKed
and all transmission requests
result in a NAK handshake.
VALID: this endpoint is enabled
(if an address match occurs, the
USB interface handles the
transaction).
Meaning