ST72651AR6 STMicroelectronics, ST72651AR6 Datasheet - Page 90

• Manufacturer Part Number: ST72651AR6
• Description: LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI
• Manufacturer: STMicroelectronics

Specifications of ST72651AR6

• Dual Supply Management: analog voltage detector on the USB power line to enable smart power switching from USB power to battery (on E suffix devices).
• Programmable Internal Voltage Regulator For Memory Cards (2.8v To 3.5v) Supplying: Flash Card I/O lines (voltage shifting)
• 5 Usb Endpoints: 1 control endpoint
• Dtc (data Transfer Coprocessor): Universal Serial/Parallel communications interface, with software plug-ins for current and future protocol standards

ST72651AR6
PWM/BRM GENERATOR (Cont’d)
BRM Generation
The BRM bits allow the addition of a pulse to wid-
en a standard PWM pulse for specific PWM cy-
cles. This has the effect of “fine-tuning” the PWM
Duty cycle (without modifying the base duty cycle),
thus, with the external filtering, providing additional
fine voltage steps.
The incremental pulses (with duration of T
added to the beginning of the original PWM pulse.
The PWM intervals which are added to are speci-
fied in the 4-bit BRM register and are encoded as
shown in the following table. The BRM values
shown may be combined together to provide a
summation of the incremental pulse intervals
specified.
The pulse increment corresponds to the PWM res-
olution.
For example, if
– Data 18h is written to the PWM register
– Data 06h (00000110b) is written to the BRM reg-
– with a 8MHz internal clock (125ns resolution)
Then 3.0 μs-long pulse will be output at 8 μs inter-
vals, except for cycles numbered 2,4,6,10,12,14,
where the pulse is broadened to 3.125 μs.
Figure 51. BRM pulse addition (PWM > 0)
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ister
T
m = 0
CPU
x 64
T
m = 1
CPU
x 64
CPU
Doc ID 7215 Rev 4
T
) are
CPU
T
m = 2
CPU
x 64 increment
x 64
Note. If 00h is written to both PWM and BRM reg-
isters, the generator output will remain at “0”. Con-
versely, if both registers hold data 3Fh and 0Fh,
respectively, the output will remain at “1” for all in-
tervals 1 to 15, but it will return to zero at interval 0
for an amount of time corresponding to the PWM
resolution (T
An output can be set to a continuous “1” level by
clearing the PWM and BRM values and setting
POL = “1” (inverted polarity) in the PWM register.
This allows a PWM/BRM channel to be used as an
additional I/O pin if the DAC function is not re-
quired.
Table 30. Bit BRM Added Pulse Intervals
(Interval #0 not selected).
BRM 4 - Bit Data
0000
0001
0010
0100
1000
CPU
).
none
i = 8
i = 4,12
i = 2,6,10,14
i = 1,3,5,7,9,11,13,15
Incremental Pulse Intervals
T
m = 15
CPU
x 64