ST10F276Z5 STMicroelectronics, ST10F276Z5 Datasheet - Page 172

• Manufacturer Part Number: ST10F276Z5
• Description: 16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
• Manufacturer: STMicroelectronics

Specifications of ST10F276Z5

• Single Voltage Supply: 5V ±10% (embedded regulator for 1.8 V core supply)

Register set
Note:
172/239
BUSCON0 is initialized with 0000h, if EA pin is high during reset. If EA pin is low during
reset, bit BUSACT0 and ALECTRL0 are set to ‘1’ and bit field BTYP is loaded with the bus
configuration selected via PORT0.
RP0H (F108h / 84h)
Table 81.
1. RP0H is a read-only register.
2. These bits are set according to Port 0 configuration during any reset sequence.
3. RP0H.7 to RP0H.5 bits are loaded only during a long hardware reset. As pull-up resistors are active on
EXICON (F1C0h / E0h)
WRC
CSSEL
SALSEL
CLKSEL
15
15
EXI7ES
each Port P0H pins during reset, RP0H default value is “FFh”.
RW
(2)
Bit
14
14
(2)
(2) (3)
(2)
RPOH description
13
13
EXI6ES
RW
Write configuration control
‘0’: Pin WR acts as WRL, pin BHE acts as WRH
‘1’: Pins WR and BHE retain their normal function
Chip select line selection (number of active CS outputs)
0 0: 3 CS lines: CS2...CS0
0 1: 2 CS lines: CS1...CS0
1 0: No CS line at all
1 1: 5 CS lines: CS4...CS0 (Default without pull-downs)
Segment address line selection (number of active segment address outputs)
’00’: 4-bit segment address: A19...A16
’01’: No segment address lines at all
’10’: 8-bit segment address: A23...A16
’11’: 2-bit segment address: A17...A16 (Default without pull-downs)
System clock selection
’000’: f
’001’: f
’010’: f
’011’: f
’100’: f
’101’: f
’110’: f
’111’: f
12
12
-
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
11
11
EXI5ES
= 16 x f
= 0.5 x f
= 10 x f
= f
= 5 x f
= 8 x f
= 3 x f
= 4 x f
RW
OSC
10
10
(1)
OSC
OSC
OSC
OSC
OSC
OSC
OSC
EXI4ES
9
9
RW
ESFR
ESFR
8
8
EXI3ES
7
7
Function
RW
CLKSEL
R
6
6
EXI2ES
5
5
RW
SALSEL
4
4
R
EXI1ES
3
3
RW
Reset value: 0000h
Reset value: --XXh
2
2
CSSEL
ST10F276Z5
R
EXI0ES
1
1
RW
WRC
R
0
0