ST10F276Z5 STMicroelectronics, ST10F276Z5 Datasheet - Page 32
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ST10F276Z5
Manufacturer Part Number
ST10F276Z5
Description
16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
Manufacturer
STMicroelectronics
Datasheet
1.ST10F276Z5.pdf
(239 pages)
Specifications of ST10F276Z5
Single Voltage Supply
5V ±10% (embedded regulator for 1.8 V core supply)
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Internal Flash memory
4.4.3
32/239
Flash control register 1 low
The Flash control register 1 low (FCR1L), together with Flash control register 1 high
(FCR1H), is used to select the sectors to erase, or during any write operation to monitor the
status of each sector of the module selected by SMOD bit of FCR0H. First diagram shows
FCR1L meaning when SMOD=0; the second one when SMOD=1.
FCR1L (0x0E 0004) SMOD=0
FCR1L (0x0E 0004) SMOD=1
Table 9.
SMOD=0 (XFLASH selected)
B2F(2:0)
SMOD=1 (IFLASH selected)
B0F(9:0)
15
15
Bit
14
14
Reserved
Flash control register 1 low
13
13
Bank 2 XFLASH sector 2:0 status
These bits must be set during a Sector Erase operation to select the sectors to erase
in bank 2. Besides, during any erase operation, these bits are automatically set and
give the status of the 3 sectors of bank 2 (B2F2-B2F0). The meaning of B2Fy bit for
sector y of bank 2 is given by the next Table 11. These bits are automatically reset at
the end of a write operation if no errors are detected.
Bank 0 IFLASH sector 9:0 status
These bits must be set during a Sector Erase operation to select the sectors to erase
in bank 0. Besides, during any erase operation, these bits are automatically set and
give the status of the 10 sectors of bank 0 (B0F9-B0F0). The meaning of B0Fy bit for
sector y of bank 0 is given by the next
the end of a Write operation if no errors are detected.
12
12
11
11
10
10
Reserved
B0F9 B0F8 B0F7 B0F6 B0F5 B0F4 B0F3 B0F2 B0F1 B0F0
RS
9
9
FCR
FCR
RS
8
8
RS
7
7
Function
Table
RS
11. These bits are automatically reset at
6
6
RS
5
5
RS
4
4
RS
3
3
Reset value: 0000h
Reset value: 0000h
B2F2 B2F1 B2F0
RS
RS
2
2
ST10F276Z5
RS
RS
1
1
RS
RS
0
0
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