ST10F276Z5 STMicroelectronics, ST10F276Z5 Datasheet - Page 200

• Manufacturer Part Number: ST10F276Z5
• Description: 16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
• Manufacturer: STMicroelectronics

Specifications of ST10F276Z5

• Single Voltage Supply: 5V ±10% (embedded regulator for 1.8 V core supply)

Electrical characteristics
23.8.8
200/239
Due to this adaptation to the input clock, the frequency of f
locked to f
individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated
using the minimum TCL that is possible under the respective circumstances.
The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes f
keep it locked on f
one TCL period.
This is especially important for bus cycles using wait states and e.g. for the operation of timers,
serial interfaces, etc. For all slower operations and longer periods (such as, for example, pulse
train generation or measurement, lower baud rates) the deviation caused by the PLL jitter is
negligible. Refer to next
Voltage controlled oscillator
The ST10F276Z5 implements a PLL which combines different levels of frequency dividers
with a Voltage Controlled Oscillator (VCO) working as frequency multiplier. The following
table presents a detailed summary of the internal settings and VCO frequency.
Table 98.
The PLL input frequency range is limited to 1 to 3.5 MHz, while the VCO oscillation range is
64 to 128 MHz. The CPU clock frequency range when PLL is used is 16 to 64 MHz.
Example 1
●
●
●
●
●
●
1
1
1
1
0
0
0
0
(P0H.7-5)
P0.15-13
1
1
0
0
1
1
0
0
F
P0(15:13) = ‘110’ (multiplication by 3)
PLL input frequency = 2.5 MHz
VCO frequency = 120 MHz
PLL output frequency = 30 MHz
(VCO frequency divided by 4)
F
XTAL
CPU
1
0
1
0
1
0
1
0
XTAL
= 30 MHz (no effect of output prescaler)
= 10 MHz
4 to 8 MHz
5.3 to
10.6 MHz
4 to 8 MHz
6.4 to 12 MHz F
1 to 64 MHz
4 to 6.4 MHz
4 to 12 MHz
4 MHz
Internal PLL divider mechanism
frequency
. The slight variation causes a jitter of f
XTAL
XTAL
. The relative deviation of TCL is the maximum when it is referred to
Section 23.8.9: PLL Jitter
F
F
F
–
F
–
F
prescaler
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
Input
/ 4
/ 4
/ 4
/ 4
/ 2
/ 2
Multiply by
64
48
64
40
40
64
PLL bypassed
PLL bypassed
PLL
for more details.
Divide by
CPU
4
4
2
2
2
2
which also effects the duration of
CPU
is constantly adjusted so it is
prescaler
F
Output
PLL
–
–
–
–
–
–
–
/ 2
f
CPU frequency
CPU
F
F
ST10F276Z5
F
F
F
F
F
F
XTAL x 10
XTAL x 16
= f
XTAL x 4
XTAL x 3
XTAL x 8
XTAL x 5
XTAL x 1
XTAL / 2
CPU
XTAL
to
x F