FAN6921MR Fairchild Semiconductor, FAN6921MR Datasheet

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FAN6921MR

Manufacturer Part Number
FAN6921MR
Description
The highly integrated FAN6921MR combines Power Factor Correction (PFC) controller and Quasi-Resonant PWM controller
Manufacturer
Fairchild Semiconductor
Datasheet

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© 2009 Fairchild Semiconductor Corporation
FAN6921MR Rev. 1.0.2
FAN6921MR
Integrated Critical Mode PFC and Quasi-Resonant
Current Mode PWM Controller
Features
Applications
Ordering Information
FAN6921MRMY
Part Number
Integrated PFC and Flyback Controller
Critical Mode PFC Controller
Zero-Current Detection for PFC Stage
Quasi-Resonant Operation for PWM Stage
Internal Minimum t
Internal 10ms Soft-Start for PWM
Brownout Protection
High / Low Line Over-Power Compensation
Auto-Recovery Over-Current Protection
Auto-Recovery Open-Loop Protection
Externally Latch Triggering (RT Pin)
Adjustable Over-Temperature Latched (RT Pin)
VDD Pin and Output Voltage OVP (Latched)
Internal Over-Temperature Shutdown (140°C)
AC/DC NB Adapters
Open-Frame SMPS
Battery Charger
Recovery
OFF
Mode
OLP
8µs for QR PWM Stage
Temperature Range
-40°C to +105°C
Operating
Description
The highly integrated FAN6921MR combines Power
Factor Correction (PFC) controller and Quasi-Resonant
PWM controller. Integration provides cost effect design
and allows for fewer external components.
For PFC, FAN6921MR uses a controlled on-time
technique to provide a regulated DC output voltage and
to perform natural power factor correction. With an
innovative THD optimizer, FAN6921MR can reduce
input current distortion at zero-crossing duration to
improve THD performance.
For PWM, FAN6921MR provides several functions to
enhance
detection, green-mode operation, high / low line over
power compensation. FAN6921MR provides many
protection functions as well: secondary-side open-loop
and over-current with auto recovery protection, external
latch triggering, adjustable over-temperature protection
by RT pin and external NTC resistor, internal over-
temperature shutdown, V
voltage for output OVP, and brown-in / out for AC input
voltage UVP.
The FAN6921MR controller is available in a 16-pin small
outline package (SOP).
16-Pin Small Outline Package (SOP)
the
Package
power
system
DD
pin OVP, and DET pin over-
performance:
June 2011
Tape & Reel
www.fairchildsemi.com
Packing
Method
valley

FAN6921MR Summary of contents

Page 1

... RT pin and external NTC resistor, internal over- temperature shutdown, V voltage for output OVP, and brown-in / out for AC input voltage UVP. The FAN6921MR controller is available in a 16-pin small outline package (SOP). Operating Temperature Range -40°C to +105°C ...

Page 2

... Application Diagram © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.2 Figure 1. Typical Application 2 www.fairchildsemi.com ...

Page 3

... Internal Block Diagram © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.2 Figure 2. Functional Block Diagram 3 www.fairchildsemi.com ...

Page 4

... CSPWM pin for the cycle-by-cycle current limit, current- mode control, and high / low line over-power compensation according to DET pin source current during PWM t © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.2 Figure 3. Marking Diagram Figure 4. Pin Configuration time. ...

Page 5

... PFC switching. This can be realized with an external circuit if disabling the PFC stage is desired connection High-voltage startup. HV pin is connected to the AC line voltage through a resistor 16 HV (100kΩ t ypical) for providing a high charging current to V © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.2 capacitor www.fairchildsemi.com ...

Page 6

... The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol T Operating Ambient Temperature A © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.2 Parameter (3) (3) Parameter 6 Min. Max. ...

Page 7

... Range-Enable/ Disable Debounce t RANGE Time V Output Low Voltage of RANGE Pin I RANGE-OL Output High Leakage Current of I RANGE-OH RANGE Pin t PFC Maximum On Time ON-MAX-PFC © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0 unless otherwise specified. J Conditions 0.16V, DD DD-ON Gate Open V =15V, DD OPFC, OPWM=100kHz, ...

Page 8

... PFC Current Sense Section Threshold Voltage for Peak V CSPFC Current Cycle-by-Cycle Limit t Propagation Delay PD t Leading-Edge Blanking Time BNK CSPFC Compensation Ratio for A V THD © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.2 (Continued unless otherwise specified. J Conditions (4) RANGE=Open RANGE=Ground INVH REF RANGE=Open (4) ...

Page 9

... Restart Time RESTART-PFC Inhibit Time (Maximum Switching t INHIB Frequency Limit) PFC Enable/ Disable Function V ZCD-DIS Threshold Voltage PFC Enable/ Disable Function t ZCD-DIS Debounce Time © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.2 (Continued unless otherwise specified. J Conditions V = 25V DD V =15V, I =100mA ...

Page 10

... Minimum Off Time OFF-MIN Beginning of Green-On Mode Voltage Level Beginning of Green-Off Mode Voltage Level Hysteresis for Beginning of ΔV Green-Off Mode at FB Voltage G Level © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.2 (Continued unless otherwise specified. J Conditions CSPWM 0<V <0.9 CSPWM (4) FB>V ...

Page 11

... Leading-Edge Blanking Time ON-BNK CSPWM Pin Floating V V CS-FLOATING Clamped High Voltage The Delay Time once CSPWM t CS-H Pin Floating © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.2 (Continued) ), unless otherwise specified. J Conditions RANGE Pin Internally Open RANGE Pin Internally Ground RANGE Pin Internally Open ...

Page 12

... Threshold Voltage for Two-level V RT-OTP-LEVEL Debounce Time t Debounce Time for OTP RT-OTP-H Debounce Time for Externally t RT-OTP-L Triggering Note: 4. Guaranteed by design. © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.2 (Continued) ), unless otherwise specified. J Conditions V <V RT RT-OTP-LEVEL 12 Min. Typ. Max. Units 125 140 ...

Page 13

... Temperature( Figure 9. Startup Current 2.60 2.55 2.50 2.45 2.40 -40 -25 - Temperature( Figure 11. PFC Output Feedback Reference Voltage © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.2 =25° 110 125 110 125 o C) Figure 110 125 ...

Page 14

... Temperature( Figure 17. Beginning of Green-On Mode at V 9.0 8.5 8.0 7.5 7.0 -40 -25 - Temperature( Figure 19. PWM Minimum Off-Time for V © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.2 (Continued) =25° 110 125 o C) Figure 14. PFC Peak Current Limit Voltage 50.0 48.0 46.0 44.0 42.0 40 110 125 ...

Page 15

... Figure 21. Lower Clamp Voltage of DET Pin 110 105 100 95 90 -40 -25 - Temperature( Figure 23. Internal Source Current of RT Pin © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.2 (Continued) =25° 110 125 o C) Figure 22. Reference Voltage for Output Over ...

Page 16

... Multi-Vector Error Amplifier and THD Optimizer For better dynamic performance, faster transient response, and precise clamping on PFC output, FAN6921MR uses a trans-conductance type amplifier with proprietary innovative multi-vector error amplifier. The schematic diagram of this amplifier is shown in Figure 25. The PFC output voltage is detected from the ...

Page 17

... Figure 31. Operation Waveforms of PFC Zero- Protection for PFC Stage PFC Output Voltage UVP and OVP (INV Pin) FAN6921MR provides several kinds of protection for PFC stage. PFC output over- and under-voltage are essential for PFC stage. Both are detected and determined by INV pin voltage, as shown in Figure 32. ...

Page 18

... CSPFC OPFC Figure 33. Cycle-by-Cycle Current Limiting Brown-In / Out Protection (VIN Pin) With AC voltage detection, FAN6921MR can perform brown-in/ out protection (AC voltage UVP). Figure 34 shows the key operation waveforms of brown-in / out protection. Both use the VIN pin to detect AC input voltage level and the VIN pin is connected to AC input by a resistor divider (refer to Figure 1) ...

Page 19

... When the drain voltage on the PWM switch falls, the voltage across on auxiliary winding V also decreases since auxiliary winding is coupled to primary winding. Once the V falls to negative, V (refer to Figure 39) and FAN6921MR is forced to flow out a current I this I DET threshold current, PWM gate signal is sent out after a ...

Page 20

... DET of the output diode and C AUX prevent this spike, a leading-edge blanking time is built- DET in to FAN6921MR and a small RC filter is also recommended between the CSPWM pin and GND (e.g. 100Ω, 470pF). 20 becomes higher as well as AUX ...

Page 21

... PWM transformer inductor; the voltage across on auxiliary winding is reflected from secondary winding and therefore the flat voltage on the DET pin is proportional to the output voltage. FAN6921MR can sample this flat voltage level after a t perform output over-voltage protection. This t blanking time is used to ignore the voltage ringing from leakage inductance of PWM transformer ...

Page 22

... Open-Loop, Short-Circuit, and Overload Protection (FB Pin) Figure 45. FB Pin Open-Loop, Short Circuit, and Overload Protection Referring to Figure 45, outside of FAN6921MR, the FB pin is connected to the collector of transistor of an opto- coupler. Inside of FAN6921MR, the FB pin is connected to an internal voltage bias through a resistor around 5k. ...

Page 23

... Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/, © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.2 Figure 46. 16-Pin Small Outline Package (SOIC) 23 www.fairchildsemi.com ...

Page 24

... Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.2 24 www.fairchildsemi.com ...

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