FAN6921MR Fairchild Semiconductor, FAN6921MR Datasheet - Page 5

• Manufacturer Part Number: FAN6921MR
• Description: The highly integrated FAN6921MR combines Power Factor Correction (PFC) controller and Quasi-Resonant PWM controller
• Manufacturer: Fairchild Semiconductor

© 2009 Fairchild Semiconductor Corporation
FAN6921MR Rev. 1.0.2
Pin Definitions
Pin #
10
11
12
13
14
15
16
6
7
8
9
OPWM
Name
OPFC
GND
VDD
ZCD
DET
VIN
NC
FB
RT
HV
The power ground and signal ground.
Description
Totem-pole driver output to drive the external power MOSFET. The clamped gate output voltage
is 15.5V.
Power supply. The threshold voltage for startup and turn-off is 18V and 7.5V, respectively. The
startup current is less than 30µA and the operating current is lower than 10mA.
Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped
gate output voltage is 17.5V.
This pin is connected to an auxiliary winding of the PWM transformer through a resistor divider for
the following purposes:
Feedback voltage pin. This pin is used to receive output voltage level signal to determine PWM
gate duty for regulating output voltage. The FB pin voltage can also activate open-loop, over-load
protection, and output-short circuit protection if the FB pin voltage is higher than a threshold of
around 4.2V for more than 50ms.The input impedance of this pin is a 5kΩ e quivalent resistance. A
1/3 attenuator is connected between the FB pin and the input of the CSPWM/FB comparator.
Adjustable over-temperature protection and external latch triggering. A constant current is flowed
out of the RT pin. When RT pin voltage is lower than 0.8V (typical), latch mode protection is
activated and stops all PFC and PWM switching operation until the AC plug is removed.
Line-voltage detection for brown-in / out protections. This pin can receive the AC input voltage
level through a voltage divider. The voltage level of the VIN pin is not only used to control
RANGE pin’s status, but it can also perform brown-in / out protection for AC input voltage UVP.
Zero-current detection for the PFC stage. This pin is connected to an auxiliary winding coupled to
PFC inductor winding to detect the ZCD voltage signal once the PFC inductor current discharges
to zero. When the ZCD voltage signal is detected, the controller starts a new PFC switching
cycle. When the ZCD pin voltage is pulled to under 0.2V (typical), it disables the PFC stage and
the controller stops PFC switching. This can be realized with an external circuit if disabling the
PFC stage is desired.
No connection
High-voltage startup. HV pin is connected to the AC line voltage through a resistor
(100kΩ t ypical) for providing a high charging current to V
 Producing an offset voltage to compensate the threshold voltage of PWM current limit for
 Detecting the valley voltage signal of drain voltage of the PWM switch to achieve the valley
 Providing output over-voltage protection. A voltage comparator is built-in to the DET pin. The
(Continued)
providing over-power compensation. The offset is generated in accordance with the input
voltage when PWM switch is on.
voltage switching and minimize the switching loss on PWM switch.
DET pin detects the flat voltage through a voltage divider paralleled with auxiliary winding. This
flat voltage is reflected to the secondary winding during PWM inductor discharge time. If output
OVP and this flat voltage is higher than 2.5V, the controller enters latch mode and stops all
PFC and PWM switching operation.
5
DD
capacitor.
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