FDMS3660S Fairchild Semiconductor, FDMS3660S Datasheet
FDMS3660S
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FDMS3660S Summary of contents
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... Package Marking and Ordering Information Device Marking Device 22CF FDMS3660S 07OD ©2011 Fairchild Semiconductor Corporation FDMS3660S Rev.C1 General Description This device includes two specialized N-Channel MOSFETs in a dual PQFN package. The switch node has been internally = connected to enable easy placement and routing of synchronous ...
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... Q Total Gate Charge g Q Total Gate Charge g Q Gate to Source Gate Charge gs Q Gate to Drain “Miller” Charge gd ©2011 Fairchild Semiconductor Corporation FDMS3660S Rev. °C unless otherwise noted J Test Conditions = 250 μ mA 250 μ ...
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... As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied with the negative Vgs rating based on starting based on starting ©2011 Fairchild Semiconductor Corporation FDMS3660S Rev. °C unless otherwise noted J Test Conditions ...
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... PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 150 1.5 2.0 2 GATE TO SOURCE VOLTAGE (V) GS Figure 5. Transfer Characteristics ©2011 Fairchild Semiconductor Corporation FDMS3660S Rev. °C unless otherwise noted μ s 0.6 0.8 1 100 125 150 -55 ...
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... MAX RATED 0 125 C/W θ 0.01 0.01 0 DRAIN to SOURCE VOLTAGE (V) DS Figure 11. Forward Bias Safe Operating Area ©2011 Fairchild Semiconductor Corporation FDMS3660S Rev. °C unless otherwise noted 100 C J ...
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... Typical Characteristics (Q1 N-Channel) 2 DUTY CYCLE-DESCENDING ORDER 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 0.001 - Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2011 Fairchild Semiconductor Corporation FDMS3660S Rev. °C unless otherwise noted J SINGLE PULSE 125 C/W θ JA (Note 1c RECTANGULAR PULSE DURATION (sec) 6 ...
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... DUTY CYCLE = 0.5% MAX 100 125 1.0 1.5 2 GATE TO SOURCE VOLTAGE (V) GS Figure 18. Transfer Characteristics ©2011 Fairchild Semiconductor Corporation FDMS3660S Rev. unlenss otherwise noted J μ s 0.6 0.8 1.0 Figure 15. Normalized on-Resistance vs Drain 50 75 100 125 150 ...
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... T = MAX RATED 0 120 C/W θ 0.01 0.01 0 DRAIN to SOURCE VOLTAGE (V) DS Figure 24. Forward Bias Safe Operating Area ©2011 Fairchild Semiconductor Corporation FDMS3660S Rev. unless otherwise noted 100 100 1000 μ ...
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... Typical Characteristics (Q2 N-Channel) 2 DUTY CYCLE-DESCENDING ORDER 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 0.001 0.0001 - Figure 26. Junction-to-Ambient Transient Thermal Response Curve ©2011 Fairchild Semiconductor Corporation FDMS3660S Rev. unless otherwise noted J SINGLE PULSE 120 C/W θ JA (Note 1d RECTANGULAR PULSE DURATION (sec) ...
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... TIME (ns) Figure 27. FDMS3660S SyncFET body diode reverse recovery characteristic ©2011 Fairchild Semiconductor Corporation FDMS3660S Rev.C1 (continued) Schottky barrier diodes exhibit significant leakage at high tem- perature and high reverse voltage. This will increase the power in the device μ ...
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... As shown in the figure 29, the Power Stage solution rings significantly less than competitor solutions under the same set of test conditions. Power Stage Device Figure 29. Power Stage phase node rising edge, High Side Turn on *Patent Pending ©2011 Fairchild Semiconductor Corporation FDMS3660S Rev.C1 Competitors solution 11 www.fairchildsemi.com ...
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... Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2), should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout proce- dure is discussed below to maximize the electrical and thermal performance of the part. ©2011 Fairchild Semiconductor Corporation FDMS3660S Rev.C1 Figure 31. Recommended PCB Layout 12 www.fairchildsemi.com ...
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... Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected from the backside via a network of low inductance vias. ©2011 Fairchild Semiconductor Corporation FDMS3660S Rev.C1 13 www.fairchildsemi.com ...
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... Dimensional Outline and Pad Layout 0. PKG PIN #1 IDENT MAY APPEAR AS OPTIONAL 0.35 6X 3.90 3.70 0.58 0.38 0.44 0.24 0.10 C 0.08 C 1.10 0.90 ©2011 Fairchild Semiconductor Corporation FDMS3660S Rev.C1 5.10 4.90 A PKG 6. 5.90 2.15 4.16 2.13 0. TOP VIEW 0.63 SEE DETAIL A RECOMMENDED LAND PATTERN SIDE VIEW 0.10 3.00 0.58 0.70 0.05 0.38 2.80 0.50 1. 1.12 0.71 0.61 NOTES: UNLESS OTHERWISE SPECIFIED 2.25 2.05 A) DOES NOT FULLY CONFORM TO JEDEC REGISTRATION, MO-240, ISSUE B DATED 10/2009 ...
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... Datasheet Identification Product Status Advance Information Formative / In Design Preliminary First Production No Identification Needed Full Production Obsolete Not In Production ©2011 Fairchild Semiconductor Corporation FDMS3660S Rev.C1 ® PowerTrench PowerXS™ SM Programmable Active Droop™ ® QFET QS™ Quiet Series™ RapidConfigure™ ™ ...