HFA3863IN96 Intersil Corporation, HFA3863IN96 Datasheet - Page 13

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HFA3863IN96

Manufacturer Part Number
HFA3863IN96
Description
Processor, Direct Sequence Spread Spectrum Base band Processor with Rake Receiver and Equalizer, Tape And Reel
Manufacturer
Intersil Corporation
Datasheet
as the AGC state machine runs asynchronously with respect
to slot times.
SQ1 becomes active only when a spread signal with the
proper PN code has been detected, and the peak correlation
amplitude to sidelobe ratio exceeds a set threshold, so it
may not be adequate in itself.
A SQ1 evaluation occurs whenever the AGC has remained
locked for the entire data ingest period. When this happens,
SQ1 is updated between 8 and 9µs into the 10µs dwell. If
CS1 is not active, two consecutive SQ1s are required to
advance the part to tracking.
The state of CCA is not guaranteed from the time RX_PE
goes high until the first CCA assessment is made. At the end
of a packet, after RXPE has been deasserted, the state of
CCA is also not guaranteed.
The receive signal strength indication (RSSI) measurement is
derived from the state of the AGC circuit. ED is the
comparison result of RSSI against a threshold. The threshold
may be set to an absolute power value, or it may be set to be
N dB above the measured noise floor. See CR 35. The
HFA3863 measures and stores the RSSI level when it detects
no presence of BPSK or QPSK signals. The average value of
a 256 value buffer is taken to be the noise floor. Thus, the
value of the noise floor will adapt to the environment. A
separate noise floor value is maintained for each antenna. An
initial value of the noise floor is established within 50µs of the
chip being active and is refined as time goes on. Deasserting
RX_PE does not corrupt the learned values. If the absolute
power metric is chosen, this threshold is normally set to
between -70 and -80dBm.
If desired, ED may be used in the acquisition process as well
as CCA. ED may be used to mask (squelch) weak signals
and prevent radio reception of signals too weak to support
the high data rates, signals from adjacent cells, networks, or
buildings.
The Configuration registers effecting the CCA algorithm
operation are summarized below (more programming details
on these registers can be found under the Control Registers
section of this document).
The CCA output from pin 60 of the device can be defined as
active high or active low through CR 1 (bit 2).
CR9(6:5) allow CCA to be programmed to be a function of
ED only, the logical operation of (CS1 OR SQ1), the logical
function of (ED AND (CS1 OR SQ1)), or (ED OR (CS1 OR
SQ1)).
CR9(7) lets the user select from sampled CCA mode, which
means CCA will not glitch, is updated once per symbol and
is valid for reading at 15.8µs or 18.7µs. In non-sampled
mode, CCA may change at any time, potentially several
times per slot, as ED and CS1 operate asynchronously to
slot times.
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HFA3863
In a typical system CCA will be monitored to determine when
the channel is clear. Once the channel is detected busy,
CCA should be checked periodically to determine if the
channel becomes clear. Once MD_RDY goes active, CCA
should be ignored for the remainder of the message. Failure
to monitor CCA until MD_RDY goes active (or use of a time-
out circuit) could result in a stalled system as it is possible for
the channel to be busy and then become clear without an
MD_RDY occurring.
AGC Description
The AGC system consists of the 3 chips handling the receive
signal, the RF to IF downconverter HFA3683, the IF to
baseband converter HFA3783, and the baseband processor.
The AGC loop (Figure 6) is digitally controlled by the BBP.
Basically it operates as follows:
Initially, the receiver is set for high gain. The percent of time
that the A/D converters in the baseband processor are
saturated is monitored along with signal amplitude and the
gain is adjusted down until the amplitude is what will
optimize the demodulator’s performance. If the amount of
saturation is great, the initial gain adjust steps are large. If
the signal overload is small, they are less. When the gain is
about right and the A/Ds’ outputs are within the lock window
(CR19), the BBP declares AGC lock and stops adjusting for
the duration of the packet. If the signal level then varies more
than a preset amount (CR20, CR29), the AGC is declared
unlocked and the gain again allowed to readjust.
The BBP looks for the locked state following an unlocked
state (CS1) as one indication that a received signal is on the
antenna. This starts the receive process of looking for PN
correlation (SQ1). Once PN correlation and AGC lock are
found, the processor begins acquisition.
For large signals, the power level in the RF stage output is
also monitored and if it is large, the LNA stage is shut down.
This removes 30dB of gain from the receive chain which is
compensated for by replacing 30dB of gain in the IF AGC
stage. There is some hysteresis in this operation and once
the AGC locks, it is locked as well. This improves the
receiver dynamic range.
rxRfAGC Pad Operation
30dB Pad Engaging (RF Chip Low Gain):
If the AGC is not locked onto a packet, a '1' on the
ifCompDet input will engage in the 30dB attenuation pad.
This causes the AGC to go out of lock and also forces the
attenuation accumulator to be set to the programmed value
of CR27. The AGC then attempts to lock on the signal.
If the AGC is locked on a packet, ifCompDet is ignored.

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