HFA3863IN96 Intersil Corporation, HFA3863IN96 Datasheet - Page 32

• Manufacturer Part Number: HFA3863IN96
• Description: Processor, Direct Sequence Spread Spectrum Base band Processor with Rake Receiver and Equalizer, Tape And Reel
• Manufacturer: Intersil Corporation

Bit 7:6
Bit 5:0
Bit 7:6
Bit 5:0
Bit 7:6
Bit 5:0
Bit 7:6
Bit 5:0
Bits 7:0
Bit 7
Bit 6
Bits 5:0
Bit 7
Bit 6
Bits 5:0
Bit 7
Bit 6:0
Bit 7
Bits 6:0
Bit 7:0
CONFIGURATION REGISTER ADDRESS 49 (62h) R/W SCRAMBLER SEED AND READ ONLY REGISTER MUX CONTROL
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Preamble Lead Coefficient (0–4 range) (000000–100000).
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Preamble Lag Coefficient (0–4 range) (000000–100000).
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Header Lead Coefficient (0–4 range) (000000–100000).
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Header Lag Coefficient (0-4 range) (000000 - 100000).
False alarm rate of SQ1. Enable/disable with CR47 bit 7.
Rate = N*32/2^16. For example 01h = 0.05% False Alarm Rate (FAR) and 10h = 0.78% FAR.
Long Preamble timeline disable.
0 = enable long preamble timeline processing.
1 = disable long preamble timeline processing (process all preambles as if short).
Long Preamble timeline diversity metric selection.
0 = H factors.
1 = RSSI.
SQ1 threshold #2, range 0 to 7.875. (000.00–111.111).
Used for verify cycle.
Disable False alarm Rate Processing.
0 = Enable, SQ1 #1 threshold is adjusted in real time by FAR logic.
1 = Disable, SQ1 #1 threshold is set to value of CR 47 (5:0).
ED and SQ2 control for acquisition.
0 = SQ1.
1 = ED and SQ1.
SQ1 threshold #1, range 0 to 7.875. (000.00–111.111).
Used for initial detect and initial setting for FAR.
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Scrambler seed for long preamble. Bit 3 of CR5 selects CR48 or CR49.
Read only register mux control.
0 = READ ONLY registers read ‘b’ value.
1 = READ ONLY registers read ‘a’ value.
Scrambler seed for short preamble. Bit 3 of CR5 selects CR48 or CR49.
a&b: reads value on test bus.
CONFIGURATION REGISTER ADDRESS 41 (52h) R/W PREAMBLE/HEADER LEAD COEFFICIENT
CONFIGURATION REGISTER ADDRESS 42 (54h) R/W PREAMBLE/HEADER LAG COEFFICIENT
CONFIGURATION REGISTER ADDRESS 48 (60h) R/W SCRAMBLER SEED, LONG PREAMBLE
CONFIGURATION REGISTER ADDRESS 45 (5Ah) R/W FALSE ALARM RATE OF SQ1
CONFIGURATION REGISTER ADDRESS 47 (5Eh) R/W ACQUISITION THRESHOLDS
CONFIGURATION REGISTER ADDRESS 43 (56h) R/W MPDU LEAD COEFFICIENT
CONFIGURATION REGISTER ADDRESS 44 (58h) R/W MPDU LAG COEFFICIENT
CONFIGURATION REGISTER ADDRESS 46 (5Ch) R/W ACQUISITION TIMELINE
32
CONFIGURATION REGISTER ADDRESS 50 (64h) R TEST BUS READ
HFA3863