HFA3863IN96 Intersil Corporation, HFA3863IN96 Datasheet - Page 19
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HFA3863IN96
Manufacturer Part Number
HFA3863IN96
Description
Processor, Direct Sequence Spread Spectrum Base band Processor with Rake Receiver and Equalizer, Tape And Reel
Manufacturer
Intersil Corporation
Datasheet
1.HFA3863IN96.pdf
(39 pages)
Data Demodulation in the CCK Modes
In this mode, the demodulator uses complementary code
keying (CCK) modulation for the two highest data rates. It is
slaved to the low rate processor which it depends on for
acquisition of initial timing and phase tracking information.
The low rate section acquires the signal, locks up symbol
and carrier tracking loops, and determines the data rate to
be used for the MPDU data.
The demodulator for the CCK modes takes over when the
preamble and header have been acquired and processed.
On the last bit of the header, the phase of the signal is
captured and used as a phase reference for the high rate
differential demodulator.
The signal from the A/D converters is carrier frequency and
phase corrected by a DESPIN stage. This removes the
frequency offset and aligns the I and Q Channels properly for
the correlators. The sample rate is decimated to 11MSPS for
the correlators after the DESPIN since the data is now
synchronous in time.
The demodulator knows the symbol timing, so the
correlation is batch processed over each symbol. The
correlation outputs from the correlator are compared to each
other in a biggest picker and the chosen one determines 6
bits of the symbol. The QPSK phase of the chosen one
determines two more bits for a total of eight bits per symbol.
Six bits come from which of the 64 correlators had the
largest output and the last two are determined from the
QPSK differential demod of that output. In the 5.5Mbps
mode, only four of the correlator outputs are monitored. This
demodulates two bits for which of four correlators had the
largest output and two more for the QPSK demodulation of
that output for a total of four bits per symbol.
Equalizer Description
The HFA3863 employs a decision feedback equalizer (DFE)
to improve performance in the presence of significant
multipath distortion. The DFE combats inter chip interference
(ICI) and inter symbol interference (ISI). The equalizer is
trained on the sample data collected during the first part of
the acquisition after the AGC has settled and the antenna
selected. The same data is used for CMF calculations and
equalizer training. Once the equalizer has been set up, it is
used to process the incoming symbols in a decision
feedback manner. After the Fast Walsh transform is
performed, the detected symbols are corrected for ICI before
the bigger picker where the symbol decision process is
performed. Once a symbol has been demodulated, the
calculated residual energy from that symbol is subtracted
from the incoming data for the next symbol. That corrects for
the ISI component. The DFE is not adapted during the
packet as the channel impulse response is not expected to
vary significantly during that brief time. Register CR10 bits 4
and 5 can disable these equalizers separately.
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HFA3863
Tracking
Carrier tracking is performed on the de-rotated signal
samples from the complex multiplier in a four phase Costas
loop. This forms the error term that is integrated in the lead/lag
filter for the NCO, closing the loop. Tracking is only measured
when there is a chip transition. Note that this tracking is
dependent on a positive SNR in the chip rate bandwidth.
The symbol clock is tracked by a sample interpolator that
can adjust the sample timing forwards and backwards by 72
increments of 1/8th chip. This approach means that the
HFA3863 can only track an offset in timing for a finite interval
before the limits of the interpolator are reached. Thus,
continuous demodulation is not possible.
Locked Oscillator Tracking
Symbol tracking can be slaved to the carrier offset tracking
for improved performance as long as at both the transmitting
and the receiving radios, the bit clocks and carrier frequency
clocks are locked to common crystal oscillators. A bit carried
in the SERVICE field (bit 2) indicates whether or not the
transmitter has locked clocks. When the same bit is set at
the receiver (CR6 bit 2), the receiver knows it can track the
bit clock by counting down the carrier tracking offset. This is
much more accurate than tracking the bit clock directly.
CR33 bit 6 can enable or disable this capability.
Demodulator Performance
This section indicates the typical performance measures for
a radio design. The performance data below should be used
as a guide. In general, the actual performance depends on
the application, interference environment, RF/IF
implementation and radio component selection.
Overall Eb/N0 Versus BER Performance
The PRISM chip set has been designed to be robust and
energy efficient in packet mode communications. The
demodulator uses coherent processing for data
demodulation. The figures below show the performance of
the baseband processor when used in conjunction with the
HFA3783 IF and the PRISM recommended IF filters. Off the
shelf test equipment are used for the RF processing. The
curves should be used as a guide to assess performance in
a complete implementation.
Factors for carrier phase noise, multipath, and other
degradations will need to be considered on an
implementation by implementation basis in order to predict
the overall performance of each individual system.
Figure 14 shows the curves for theoretical DBPSK/DQPSK
demodulation with coherent demodulation and
descrambling as well as the PRISM performance measured
for DBPSK and DQPSK. The theoretical performance for
DBPSK and DQPSK are the same as shown on the
diagram. Figure 15 shows the theoretical and actual