HFA3863IN96 Intersil Corporation, HFA3863IN96 Datasheet - Page 9

• Manufacturer Part Number: HFA3863IN96
• Description: Processor, Direct Sequence Spread Spectrum Base band Processor with Rake Receiver and Equalizer, Tape And Reel
• Manufacturer: Intersil Corporation

For the 1 and 2Mbps modes, the transmitter accepts data
from the external source, scrambles it, differentially encodes
it as either DBPSK or DQPSK, and spreads it with the BPSK
PN sequence. The baseband digital signals are then output
to the external IF modulator.
For the CCK modes, the transmitter inputs the data and
partitions it into nibbles (four bits) or bytes (eight bits). At
5.5Mbps, it uses two of those bits to select one of four
complex spread sequences from a table of CCK sequences
and then QPSK modulates that symbol with the remaining
two bits. Thus, there are four possible spread sequences to
send at four possible carrier phases, but only one is sent.
This sequence is then modulated on the I and Q outputs.
The initial phase reference for the data portion of the packet
is the phase of the last bit of the header. At 11Mbps, one
byte is used as above where six bits are used to select one
of 64 spread sequences for a symbol and the other two are
used to QPSK modulate that symbol. Thus, the total possible
MODULATION
DQPSK
DBPSK
DATA
CCK
CCK
SYMBOL
I vs. Q
Q
RATE
RATE
DATA
CHIP
I
OUT
OUT
1 BIT ENCODED TO
A/D SAMPLE CLOCK
802.11 DSSS BPSK
(TRUE-INVERSE)
ONE OF 2 CODE
11 CHIPS
BARKER
11 MC/S
WORDS
1 MS/S
1Mbps
(MHz)
22
22
22
22
9
TABLE 4. BIT RATE TABLE EXAMPLES FOR MCLK = 44MHz
2 BITS ENCODED
TO ONE OF
4 CODE WORDS
802.11 DSSS QPSK
FIGURE 7. MODULATION MODES
TX SETUP CR 5
BITS 1, 0
BARKER
11 MC/S
1 MS/S
2Mbps
11 CHIPS
00
01
10
11
HFA3863
number of combinations of sequence and carrier phases is
256. Of these only one is sent.
The bit rate Table 4 shows examples of the bit rates and the
symbol rates and Figure 7 shows the modulation schemes.
The modulator is completely independent from the
demodulator, allowing the PRISM baseband processor to be
used in full duplex operation.
Header/Packet Description
The HFA3863 is designed to handle packetized Direct
Sequence Spread Spectrum (DSSS) data transmissions.
The HFA3863 generates its own preamble and header
information. It uses two packet preamble and header
configurations. The first is backwards compatible with the
existing IEEE802.11-1997 standard 1 and 2Mbps modes
and the second is the optional shortened mode which
maximizes throughput at the expense of compatibility with
legacy equipment.
RX SIGNAL CR 63
SPREAD FUNCTIONS
4 BITS ENCODED
BITS 7, 6
COMPLEX CCK
CODE WORDS
TO ONE OF 16
5.5Mbps CCK
00
01
10
11
1.375 MS/S
COMPLEX
11 MC/S
8 CHIPS
DATA RATE
(Mbps)
5.5
11
1
2
SPREAD FUNCTIONS
8 BITS ENCODED
TO ONE OF 256
COMPLEX CCK
CODE WORDS
11Mbps CCK
1.375 MS/S
COMPLEX
11 MC/S
8 CHIPS
SYMBOL RATE
(MSPS)
1.375
1.375
1
1