HFA3863IN96 Intersil Corporation, HFA3863IN96 Datasheet - Page 30

• Manufacturer Part Number: HFA3863IN96
• Description: Processor, Direct Sequence Spread Spectrum Base band Processor with Rake Receiver and Equalizer, Tape And Reel
• Manufacturer: Intersil Corporation

Bits 7:6
Bit 5:0
Bits 7:1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Carrier Sense 2 (CS2) scale factor (0–7.875 range) (000000–111111).
Sets the transmit power. 7 bits to DAC input, -64 to 63 range.
Note: rising edge of TXPE is required for value in CR 31 to be applied to DAC.
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Selection bit for DAC input test mode 7.
0 = Barker
1 = Low rate I/Q samples.
force high rate mode.
0 = normal.
1 = force high rate mode.
Length Field counter.
0 = disable (non-EEE802.11 systems, length field may be in bits not microseconds).
1 = enabled.
Tristate test bus and enable inputs.
0 = Normal.
1 = enable inputs on test bus.
Disable spread sequence for 1 and 2Mbps.
0 = Normal.
1 = disabled.
Disable scrambler.
0 = normal scrambler operation.
1 = scrambler disabled (taps set to 0).
PN generator enable (RX 44MHz clock).
0 = not enabled.
1 = enabled. Bit must first be written to a ‘0’ before a ‘1’ to initialize logic.
PN generator enable (RX 22MHz clock).
0 = not enabled.
1 = enabled. Bit must first be written to a ‘0’ before a ‘1’ to initialize logic.
Coherent AGC disable.
0 = normal, enabled.
1 = disable.
Time Tracking Mode.
0 = enable detection of the Service field bit showing that the carrier and bit timing are locked to the same oscillator.
1 = disable detection and force locked time tracking.
NOTE: for automatic locked time tracking operation, bit 2 of the received Service field as well as bit 2 of CR6 of the receiver
must be a “1”.
DC offset compensation control. Final digital DC input offset compensation.
0 = enable DC offset compensation.
1 = disable DC offset compensation.
Bypass I/Q A/Ds.
0 = disable bypass.
1 = 4 MSBs of I/Q data are input on test bus. TESTin 3:0 is [5:2], TESTin 7:4 is Q[5:2], LSBs are zeroed.
disable time adjust during packet. Note: this turns off bit tracking.
0 = normal.
1 = time tracking disabled (overrides bit 6 also).
CONFIGURATION REGISTER ADDRESS 30 (3Ch) R/W CARRIER SENSE 2 SCALE FACTOR
30
CONFIGURATION REGISTER 31 ADDRESS (3Eh) TX POWER CONTROL
CONFIGURATION REGISTER 32 ADDRESS (40h) R/W TEST MODES 1
CONFIGURATION REGISTER ADDRESS 33 (42h) R/W TEST MODES 2
HFA3863